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[PATCH v4 6/6] target/ppc: Better CTRL SPR implementation
From: |
Nicholas Piggin |
Subject: |
[PATCH v4 6/6] target/ppc: Better CTRL SPR implementation |
Date: |
Tue, 30 May 2023 23:25:43 +1000 |
The CTRL register is able to write bit zero, and that is reflected in a
bit field in the register that reflects the state of all threads in the
core.
TCG does not implement SMT, so this just requires mirroring that bit into
the first bit of the thread state field.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/translate.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9b7884586c..b6bab4c234 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -425,7 +425,14 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int
gprn)
void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
{
- spr_write_generic32(ctx, sprn, gprn);
+ /* This does not implement >1 thread */
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */
+ tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */
+ tcg_gen_or_tl(t1, t1, t0);
+ gen_store_spr(sprn, t1);
+ spr_store_dump_spr(sprn);
/*
* SPR_CTRL writes must force a new translation block,
--
2.40.1
- [PATCH v4 0/6] target/ppc: Assorted ppc target fixes, Nicholas Piggin, 2023/05/30
- [PATCH v4 3/6] target/ppc: Add SRR1 prefix indication to interrupt handlers, Nicholas Piggin, 2023/05/30
- [PATCH v4 1/6] target/ppc: Fix instruction loading endianness in alignment interrupt, Nicholas Piggin, 2023/05/30
- [PATCH v4 4/6] target/ppc: Implement HEIR SPR, Nicholas Piggin, 2023/05/30
- [PATCH v4 2/6] target/ppc: Change partition-scope translate interface, Nicholas Piggin, 2023/05/30
- [PATCH v4 5/6] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts, Nicholas Piggin, 2023/05/30
- [PATCH v4 6/6] target/ppc: Better CTRL SPR implementation,
Nicholas Piggin <=