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[PATCH 3/4] pnv/xive2: Allow writes to the Physical Thread Enable regist
From: |
Frederic Barrat |
Subject: |
[PATCH 3/4] pnv/xive2: Allow writes to the Physical Thread Enable registers |
Date: |
Tue, 30 May 2023 18:11:28 +0200 |
Fix what was probably a silly mistake and allow to write the Physical
Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET
variant so it went unnoticed, but there's no reason to discard a write
to the full register, it is Read-Write.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
---
hw/intc/pnv_xive2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index a75ff270ac..132f82a035 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -1294,6 +1294,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr
offset,
*/
case TCTXT_EN0: /* Physical Thread Enable */
case TCTXT_EN1: /* Physical Thread Enable (fused core) */
+ xive->tctxt_regs[reg] = val;
break;
case TCTXT_EN0_SET:
--
2.40.1