Re: [PATCH v2] ppc/pnv: Add QME region for P10

[Joel Stanley]

On Fri, 7 Jul 2023 at 07:30, Cédric Le Goater <clg@kaod.org> wrote:
>
> On 7/7/23 09:12, Joel Stanley wrote:
> > The Quad Management Engine (QME) manages power related settings for its
> > quad. The xscom region is separate from the quad xscoms, therefore a new
> > region is added. The xscoms in a QME select a given core by selecting
> > the forth nibble.
> >
> > Implement dummy reads for the stop state history (SSH) and special
> > wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
> > boots on p10.
> >
> > Power9 does not have a QME.
> >
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
>
> Nice, how about these now :
>
>
> [   24.482066616,3] Could not set special wakeup on 0:0: operation timeout.
> [   25.022003091,3] Could not set special wakeup on 0:0: operation timeout.
> [   25.073902795,3] Could not set special wakeup on 0:0: operation timeout.
>
> [ 1593.383133413,3] Could not set special wakeup on 0:0: timeout waiting for 
> SPECIAL_WKUP_DONE.
> [ 1593.435173594,3] Could not set special wakeup on 0:0: timeout waiting for 
> SPECIAL_WKUP_DONE.

Yes, something like below, except hard coding is not sufficient. We
need to pass the core state into the quad model so the qme callbacks
can keep track of the wakeup state.

From: Joel Stanley <joel@jms.id.au>
Date: Fri, 7 Jul 2023 13:37:17 +0930
Subject: [PATCH] ppc/pnv: Implement more sleep related registers

We need to get the core object into the quad callback so we can update
the sleep state.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/ppc/pnv_core.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 09eb2bf94b9e..359b341c748f 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -179,6 +179,7 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
  */

 #define PNV10_XSCOM_EC_CORE_THREAD_STATE    0x412
+#define PNV10_XSCOM_EC_RAS_STATUS           0x454

 static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
                                            unsigned int width)
@@ -190,6 +191,9 @@ static uint64_t pnv_core_power10_xscom_read(void
*opaque, hwaddr addr,
     case PNV10_XSCOM_EC_CORE_THREAD_STATE:
         val = 0;
         break;
+    case PNV10_XSCOM_EC_RAS_STATUS:
+        val = -1;
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
                       offset);
@@ -494,7 +498,12 @@ static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
 };

 #define P10_QME_SPWU_HYP 0x83c
+#define  P10_SPWU_REQ           PPC_BIT(0)
+#define  P10_SPWU_DONE          PPC_BIT(4)
+
 #define P10_QME_SSH_HYP  0x82c
+#define  P10_SSH_CORE_GATED     PPC_BIT(0)
+#define  P10_SSH_SPWU_DONE      PPC_BIT(1)

 static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr,
                                             unsigned int width)
@@ -508,8 +517,11 @@ static uint64_t pnv_qme_power10_xscom_read(void
*opaque, hwaddr addr,
      */
     switch (offset & ~0xf000) {
     case P10_QME_SPWU_HYP:
+        val = 0;
+        break;
     case P10_QME_SSH_HYP:
-        return 0;
+        val = P10_SSH_SPWU_DONE;
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
                       offset);
@@ -524,6 +536,8 @@ static void pnv_qme_power10_xscom_write(void
*opaque, hwaddr addr,
     uint32_t offset = addr >> 3;

     switch (offset) {
+    case P10_QME_SSH_HYP:
+    case P10_QME_SPWU_HYP:
     default:
         qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
                       offset);
-- 
2.40.1