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Re: [PATCH] target/ppc: Fix LQ, STQ register-pair order for big-endian


From: Richard Henderson
Subject: Re: [PATCH] target/ppc: Fix LQ, STQ register-pair order for big-endian
Date: Mon, 21 Aug 2023 08:35:31 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0

On 8/21/23 08:30, Nicholas Piggin wrote:
LQ, STQ have the same register-pair ordering as LQARX/STQARX., which is
the even (lower) register contains the most significant bits. This is
not implemented correctly for big-endian.

do_ldst_quad() has variables low_addr_gpr and high_addr_gpr which is
confusing because they are low and high addresses, whereas LQARX/STQARX.
and most such things use the low and high values for lo/hi variables.
The conversion to native 128-bit memory access functions missed this
strangeness.

Fix this by changing the if condition, and change the variable names to
hi/lo to match convention.

Cc:qemu-stable@nongnu.org
Reported-by: Ivan Warren<ivan@vmfacility.fr>
Fixes: 57b38ffd0c6f ("target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, 
STQ")
Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1836
Signed-off-by: Nicholas Piggin<npiggin@gmail.com>
---
Hi Ivan,

Thanks for your report. This gets AIX7.2 booting for me again with TCG,
if you would be able to confirm that it works there, it would be great.

Thanks,
Nick

  target/ppc/translate/fixedpoint-impl.c.inc | 16 ++++++++--------
  1 file changed, 8 insertions(+), 8 deletions(-)

Thanks for the catch.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~



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