qemu-ppc
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic
Date: Fri, 20 Oct 2023 13:30:50 +0200
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1

Hi Zhao,

On 20/10/23 07:50, Zhao Liu wrote:
Hi Philippe,

On Fri, Oct 13, 2023 at 04:00:59PM +0200, Philippe Mathieu-Daudé wrote:
Date: Fri, 13 Oct 2023 16:00:59 +0200
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Subject: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic
X-Mailer: git-send-email 2.41.0

Since v1:
- Added R-b tags
- Addressed Richard comments
- Postponed OBJECT_DECLARE_CPU_TYPE() changes

A heterogeneous machine must be able to instantiate CPUs
from different architectures.

Does this mean the different ISA cores in heterogeneous machine?

Yes. Currently the ARM target already allows you to do that
(multiple ISA cores within the same architecture), see the
xlnx-zcu102 and fby35 machines.

And is this case for TCG?

This is *only* for TCG. I expect hardware accel + TCG to be
theoretically possible, but no interest has been shown for
it. Anyhow this requires heterogeneous TCG as a first step.

In order to do that, the
common hw/ code has to access to the QOM CPU definitions
from various architecture.

About this kind of heterogeneous machine with multiple CPUs, is there
any initial configuration command line example?

I'm prototyping in plain C but our plan is to start with a
QMP prototype. Command line configuration is not an option,
we decided to ignore it. I'll describe that better in a RFC
document I should post soon.

Regards,

Phil.

I'm not sure how to configure this case...The main unsure thing is
whether the configuration is based on the granularity of the CPU
(by "-cpu") or the granularity of the core device (by "-device
xxx-core").

-Zhao





reply via email to

[Prev in Thread] Current Thread [Next in Thread]