Re: [PATCH v4 4/8] target/ppc: Move patching nip from exception handler to helper_scv

[BALATON Zoltan]

On Tue, 24 Oct 2023, Nicholas Piggin wrote:

Oops, this should have had a From: line here but it was your patch, sorry 
about the wrong headers.

Reagrds,
BALATON Zoltan

> Unlike sc, for scv a facility unavailable interrupt must be generated
> if FSCR[SCV]=0 so we can't raise the exception with nip set to next
> instruction but we can move advancing nip if the FSCR check passes to
> helper_scv so the exception handler does not need to change it.
>
> [balaton: added commit message]
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/excp_helper.c | 2 +-
> target/ppc/translate.c   | 6 +++++-
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 22361b6c17..dd08efe4f2 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -1405,7 +1405,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
>     case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception                     */
>         lev = env->error_code;
>         dump_syscall(env);
> -        env->nip += 4;
>         new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
>         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
>
> @@ -2528,6 +2527,7 @@ void helper_ppc_maybe_interrupt(CPUPPCState *env)
> void helper_scv(CPUPPCState *env, uint32_t lev)
> {
>     if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
> +        env->nip += 4;
>         raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev);
>     } else {
>         raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV);
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index a80d24143e..d8cd34721c 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4554,7 +4554,11 @@ static void gen_scv(DisasContext *ctx)
> {
>     uint32_t lev = (ctx->opcode >> 5) & 0x7F;
>
> -    /* Set the PC back to the faulting instruction. */
> +    /*
> +     * Set the PC back to the scv instruction (unlike sc), because a facility
> +     * unavailable interrupt must be generated if FSCR[SCV]=0. The helper
> +     * advances nip if the FSCR check passes.
> +     */
>     gen_update_nip(ctx, ctx->cia);
>     gen_helper_scv(tcg_env, tcg_constant_i32(lev));
>
> --
> 2.30.9