Re: [PATCH v8 1/3] hw/ppc: Add pnv nest pervasive common chiplet model

[Cédric Le Goater]

On 12/8/23 16:19, Chalapathi V wrote:
> A POWER10 chip is divided into logical units called chiplets. Chiplets
> are broadly divided into "core chiplets" (with the processor cores) and
> "nest chiplets" (with everything else). Each chiplet has an attachment
> to the pervasive bus (PIB) and with chiplet-specific registers. All nest
> chiplets have a common basic set of registers and This model will provide
> the registers functionality for common registers of nest chiplet (Pervasive
> Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
>
> This commit implement the read/write functions of chiplet control registers.
>
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>

Please keep the Reviewed-by tags in between versions, unless fundamental
changes were made.

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.