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[PULL 34/49] hw/ppc: N1 chiplet wiring
From: |
Nicholas Piggin |
Subject: |
[PULL 34/49] hw/ppc: N1 chiplet wiring |
Date: |
Mon, 19 Feb 2024 18:29:23 +1000 |
From: Chalapathi V <chalapathi.v@linux.ibm.com>
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 15 +++++++++++++++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0755fab155..acc4db00c1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1688,6 +1688,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
+ object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet,
+ TYPE_PNV_N1_CHIPLET);
chip->num_pecs = pcc->num_pecs;
@@ -1857,6 +1859,19 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
&chip10->homer.regs);
+ /* N1 chiplet */
+ if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE,
+ &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr);
+
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE,
+ &chip10->n1_chiplet.xscom_pb_eq_mr);
+
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE,
+ &chip10->n1_chiplet.xscom_pb_es_mr);
+
/* PHBs */
pnv_chip_power10_phb_realize(chip, &local_err);
if (local_err) {
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 0ab5c42308..9b06c8d87c 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -4,6 +4,7 @@
#include "hw/pci-host/pnv_phb4.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_homer.h"
+#include "hw/ppc/pnv_n1_chiplet.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_occ.h"
#include "hw/ppc/pnv_psi.h"
@@ -113,6 +114,7 @@ struct Pnv10Chip {
PnvOCC occ;
PnvSBE sbe;
PnvHomer homer;
+ PnvN1Chiplet n1_chiplet;
uint32_t nr_quads;
PnvQuad *quads;
--
2.42.0
- [PULL 24/49] misc/pca9552: Let external devices set pca9552 inputs, (continued)
- [PULL 24/49] misc/pca9552: Let external devices set pca9552 inputs, Nicholas Piggin, 2024/02/19
- [PULL 25/49] ppc/pnv: New powernv10-rainier machine type, Nicholas Piggin, 2024/02/19
- [PULL 26/49] ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control, Nicholas Piggin, 2024/02/19
- [PULL 27/49] ppc/pnv: Wire up pca9552 GPIO pins for PCIe hotplug power control, Nicholas Piggin, 2024/02/19
- [PULL 28/49] ppc/pnv: Use resettable interface to reset child I2C buses, Nicholas Piggin, 2024/02/19
- [PULL 31/49] ppc/pnv: Test pnv i2c master and connected devices, Nicholas Piggin, 2024/02/19
- [PULL 30/49] ppc/pnv: Add a pca9554 I2C device to powernv10-rainier, Nicholas Piggin, 2024/02/19
- [PULL 29/49] misc: Add a pca9554 GPIO device model, Nicholas Piggin, 2024/02/19
- [PULL 32/49] hw/ppc: Add pnv nest pervasive common chiplet model, Nicholas Piggin, 2024/02/19
- [PULL 33/49] hw/ppc: Add N1 chiplet model, Nicholas Piggin, 2024/02/19
- [PULL 34/49] hw/ppc: N1 chiplet wiring,
Nicholas Piggin <=
- [PULL 38/49] target/ppc: Fix move-to timebase SPR access permissions, Nicholas Piggin, 2024/02/19
- [PULL 36/49] target/ppc: Rename TBL to TB on 64-bit, Nicholas Piggin, 2024/02/19
- [PULL 35/49] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U, Nicholas Piggin, 2024/02/19
- [PULL 40/49] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, Nicholas Piggin, 2024/02/19
- [PULL 37/49] target/ppc: Improve timebase register defines naming, Nicholas Piggin, 2024/02/19
- [PULL 39/49] ppc/pnv: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/02/19
- [PULL 43/49] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/02/19
- [PULL 41/49] ppc/pnv: Implement the ChipTOD to Core transfer, Nicholas Piggin, 2024/02/19
- [PULL 42/49] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/02/19
- [PULL 44/49] target/ppc: Fix 440 tlbwe TLB invalidation gaps, Nicholas Piggin, 2024/02/19