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[PATCH] target/ppc: Add power10 pmu SPRs
From: |
Madhavan Srinivasan |
Subject: |
[PATCH] target/ppc: Add power10 pmu SPRs |
Date: |
Mon, 19 Feb 2024 16:09:24 +0530 |
Currently in tcg mode, when reading from power10 pmu spr like MMCR3,
qemu logs this message (when starting qemu with -d guest_errors)
Trying to read invalid spr 754 (0x2f2) at 0000000030056bb0
This is becuase, no read/write call-backs are registered for
these SPRs. Add support to register generic read/write
functions to these power10 pmu sprs to fix it.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
target/ppc/cpu.h | 6 ++++++
target/ppc/cpu_init.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a44de22ca4..e5d0c8a5ee 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1933,6 +1933,12 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_BOOKE_TLB2CFG (0x2B2)
#define SPR_BOOKE_TLB3CFG (0x2B3)
#define SPR_BOOKE_EPR (0x2BE)
+#define SPR_POWER_USIER2 (0x2E0)
+#define SPR_POWER_USIER3 (0x2E1)
+#define SPR_POWER_UMMCR3 (0x2E2)
+#define SPR_POWER_SIER2 (0x2F0)
+#define SPR_POWER_SIER3 (0x2F1)
+#define SPR_POWER_MMCR3 (0x2F2)
#define SPR_PERF0 (0x300)
#define SPR_RCPU_MI_RBA0 (0x300)
#define SPR_MPC_MI_CTR (0x300)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 9931372a08..d64da75a61 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5308,6 +5308,38 @@ static void register_power8_pmu_user_sprs(CPUPPCState
*env)
0x00000000);
}
+static void register_power10_pmu_sup_sprs(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR3, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIER2, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIER3, 0x00000000);
+}
+
+static void register_power10_pmu_user_sprs(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_UMMCR3, "UMMCR3",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIER2, "USIER2",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIER3, "USIER3",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
static void register_power5p_ear_sprs(CPUPPCState *env)
{
/* External access control */
@@ -6505,6 +6537,8 @@ static void init_proc_POWER10(CPUPPCState *env)
register_power9_mmu_sprs(env);
register_power10_hash_sprs(env);
register_power10_dexcr_sprs(env);
+ register_power10_pmu_sup_sprs(env);
+ register_power10_pmu_user_sprs(env);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
--
2.43.0
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