Re: [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits

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Re: [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits

From:	Cédric Le Goater
Subject:	Re: [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits
Date:	Tue, 12 Mar 2024 09:06:54 +0100
User-agent:	Mozilla Thunderbird

On 3/11/24 19:51, Nicholas Piggin wrote:

Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.

Cc: "Cédric Le Goater" <clg@kaod.org>
Cc: "Frédéric Barrat" <fbarrat@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
  hw/ppc/pnv.c   | 67 ++++++++++++++++++++++++++++++++++++++++++++++++--
  hw/ppc/spapr.c |  1 +
  2 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 52d964f77a..3e30c08420 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -332,6 +332,35 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, 
void *fdt)
      }
  }

+/*

+ * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
+ */
+static const uint8_t pa_features_300[] = { 66, 0,
+    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+    /* 6: DS207 */
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+    /* 16: Vector */
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+    /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
+    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+    /* 32: LE atomic, 34: EBB + ext EBB */
+    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+    /* 40: Radix MMU */
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+    /* 42: PM, 44: PC RA, 46: SC vec'd */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+    /* 48: SIMD, 50: QP BFP, 52: String */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+    /* 54: DecFP, 56: DecI, 58: SHA */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+    /* 60: NM atomic, 62: RNG */
+    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+};
+
  static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
  {
      static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
@@ -349,7 +378,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void 
*fdt)
          offset = pnv_dt_core(chip, pnv_core, fdt);

_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",

-                           pa_features_207, sizeof(pa_features_207))));
+                           pa_features_300, sizeof(pa_features_300))));
      }

if (chip->ram_size) {

@@ -359,6 +388,40 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, 
void *fdt)
      pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
  }

+/*

+ * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
+ * always disables copy/paste.
+ */
+static const uint8_t pa_features_31[] = { 74, 0,
+    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+    /* 6: DS207 */
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+    /* 16: Vector */
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+    /* 18: Vec. Scalar, 20: Vec. XOR */
+    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
+    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+    /* 32: LE atomic, 34: EBB + ext EBB */
+    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+    /* 40: Radix MMU */
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+    /* 42: PM, 44: PC RA, 46: SC vec'd */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+    /* 48: SIMD, 50: QP BFP, 52: String */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+    /* 54: DecFP, 56: DecI, 58: SHA */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+    /* 60: NM atomic, 62: RNG */
+    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+    /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
+    0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
+    /* 72: [P]HASHCHK */
+    0x80, 0x00,                         /* 72 - 73 */
+};
+
  static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
  {
      static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
@@ -376,7 +439,7 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, 
void *fdt)
          offset = pnv_dt_core(chip, pnv_core, fdt);

_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",

-                           pa_features_207, sizeof(pa_features_207))));
+                           pa_features_31, sizeof(pa_features_31))));
      }

if (chip->ram_size) {

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 128bfe11a8..b53c13e037 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -233,6 +233,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
                                   PowerPCCPU *cpu,
                                   void *fdt, int offset)
  {
+    /* These should be kept in sync with pnv */


yes. In that case, the array definition should be moved under target/ppc/.
May be under PowerPCCPUClass ?

Thanks,

C.

      uint8_t pa_features_206[] = { 6, 0,
          0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
      uint8_t pa_features_207[] = { 24, 0,

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Re: [PATCH 06/13] ppc/spapr: Add pa-features for POWER10 machines, (continued)
- [PATCH 07/13] ppc/pnv: Permit ibm, pa-features set per machine variant, Nicholas Piggin, 2024/03/11
  - Re: [PATCH 07/13] ppc/pnv: Permit ibm,pa-features set per machine variant, Cédric Le Goater, 2024/03/12
- [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits, Nicholas Piggin, 2024/03/11
  - Re: [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits, Cédric Le Goater <=
    - Re: [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits, Nicholas Piggin, 2024/03/12
    - Re: [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits, Cédric Le Goater, 2024/03/12
- [PATCH 09/13] target/ppc: Prevent supervisor from modifying MSR[ME], Nicholas Piggin, 2024/03/11
  - Re: [PATCH 09/13] target/ppc: Prevent supervisor from modifying MSR[ME], Harsh Prateek Bora, 2024/03/12
    - Re: [PATCH 09/13] target/ppc: Prevent supervisor from modifying MSR[ME], Nicholas Piggin, 2024/03/12
- [PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry, Nicholas Piggin, 2024/03/11
  - Re: [PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry, Harsh Prateek Bora, 2024/03/12
    - Re: [PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry, Nicholas Piggin, 2024/03/12
- [PATCH 11/13] target/ppc: Make checkstop actually stop the system, Nicholas Piggin, 2024/03/11
- [PATCH 12/13] target/ppc: improve checkstop logging, Nicholas Piggin, 2024/03/11

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