Re: [Qemu-riscv] [Qemu-devel] [PATCH 0/2] target/riscv: Bugfixes found in decodetree conversion

[Richard Henderson]

On 11/8/18 8:12 PM, Palmer Dabbelt wrote:
> * We don't take advantage of the ordering bits on fences, which could allow us
>  to emit less conservative fences.  This would presumably increase  
> performance.

Yes.

> * We treat fences as NOPs under "#ifndef CONFIG_USER_ONLY", which is a bug.

Ah yes, I'd forgotten this one.  This is a bug, in that multi-threaded user
programs do not get the memory ordering that they requested.

Hard to see, obviously, since the emulator has its own memory operations,
barriers, and locks.  But once we have a lot of the hot path of the user
program compiled, there's a lot less of that.


>     case OPC_RISC_FENCE:
> -#ifndef CONFIG_USER_ONLY
>         if (ctx->opcode & 0x1000) {
>             /* FENCE_I is a no-op in QEMU,
>              * however we need to end the translation block */
> @@ -1777,7 +1776,6 @@ static void decode_RV32_64G(CPURISCVState *env,
> DisasContext *ctx)
>             /* FENCE is a full memory barrier. */
>             tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
>         }
> -#endif
>         break;

Yes, this is minimally correct.


r~