Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true

[Markus Armbruster]

Peter Maydell <address@hidden> writes:

> On Mon, 18 Mar 2019 at 08:59, Markus Armbruster <address@hidden> wrote:
>>
>> Alistair Francis <address@hidden> writes:
>>
>> > Set msi_nonbroken as true for the PLIC.
>> >
>> > According to the comment located here:
>> > https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
>> > the msi_nonbroken variable should be set to true even if they don't
>> > support MSI. In this case that is what we are doing as we don't support
>> > MSI.
>> >
>> > Signed-off-by: Alistair Francis <address@hidden>
>> > Reported-by: Andrea Bolognani <address@hidden>
>> > Reported-by: David Abdurachmanov <address@hidden>
>> > ---
>> > This should allow working pcie-root-ports in QEMU and allow libvirt
>> > to start using PCIe by default for RISC-V guests.
>>
>> Lovely!  If more people reviewed and updated their interrupt controllers
>> this way, we'd be in better shape.
>
> Why do we have a flag which each interrupt controller
> has to set rather than just making the right thing the
> default (and having the one or two interrupt controllers
> that need the wrong thing for backwards compatibility reasons
> be the ones that have to set the flag) ? This way round makes
> it way to easy to add a new interrupt controller with this
> bug without noticing it, I think.

This is ultimately a question for Michael (cc'ed).  However, I can
provide a bit of context right away.

The problem is virtual interrupt controllers that claim to support MSI
when they don't.  The OS's probe returns "go ahead and use MSI", and the
system falls apart.

So we put in a lame work-around to masks these interrupt controller
bugs: if MSI is broken, mangle all PCI devices to make them deny MSI
capability.

The next problem is that we don't even know which of our interrupt
controllers have MSI working.  So we summarily declare them all broken,
then have the few we actually know declare themselves non-broken.

The next problem is having multiple interrupt controllers, some broken,
some not.  The work-around falls apart there.  We currently use the
ostrich algorithm to deal with that.

More information in the thread around
Message-ID: <address@hidden>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg00983.html