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[Qemu-riscv] [PATCH for 4.0 v3 0/2] Update the QEMU PLIC addresses
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [PATCH for 4.0 v3 0/2] Update the QEMU PLIC addresses |
Date: |
Thu, 4 Apr 2019 18:15:14 +0000 |
This series updates the PLIC address to match the documentation.
This fixes: https://github.com/riscv/opensbi/issues/97
V3:
- Fix SiFive U crash
V2:
- Squash patches to ensure biesctability
Alistair Francis (2):
riscv: plic: Fix incorrect irq calculation
riscv: plic: Log guest errors
hw/riscv/sifive_plic.c | 16 +++++++++++-----
include/hw/riscv/sifive_e.h | 2 +-
include/hw/riscv/sifive_u.h | 4 ++--
include/hw/riscv/virt.h | 2 +-
4 files changed, 15 insertions(+), 9 deletions(-)
--
2.21.0
- [Qemu-riscv] [PATCH for 4.0 v3 0/2] Update the QEMU PLIC addresses,
Alistair Francis <=