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Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall
From: |
Alistair Francis |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU |
Date: |
Tue, 9 Apr 2019 10:16:39 -0700 |
On Thu, Apr 4, 2019 at 5:35 AM Ian Campbell <address@hidden> wrote:
>
> On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote:
> > + for (i = 0; i < strlen(riscv_cpu); i++) {
> > + if (i == 0 && riscv_cpu[i] == 'r' &&
> > + riscv_cpu[i + 1] == 'v') {
>
> Dpes something somewhere else enforce a minimum length or can
> `riscv_cpu[i + 1]` be past the end of the string?
>
> Similarly some more times below and also for the `i += 2` bits.
Good point, a valid string must be at least 5 characters so I have
added a check before we start the parsing.
Alistair
>
> > + /* Starts with "rv" */
> > + i += 2;
> > + if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') {
> > + i += 2;
> > + valid = true;
> > + rvxlen = RV32;
> > + }
> > + if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') {
> > + i += 2;
> > + valid = true;
> > + rvxlen = RV64;
> > + }
> > + }
>
> Ian.
>