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Re: [Qemu-riscv] [PATCH v1 3/4] disas/riscv: Fix `rdinstreth` constraint
From: |
Alistair Francis |
Subject: |
Re: [Qemu-riscv] [PATCH v1 3/4] disas/riscv: Fix `rdinstreth` constraint |
Date: |
Mon, 17 Jun 2019 10:05:39 -0700 |
On Fri, Jun 14, 2019 at 2:41 AM Palmer Dabbelt <address@hidden> wrote:
>
> On Fri, 17 May 2019 15:11:04 PDT (-0700), Alistair Francis wrote:
> > From: Michael Clark <address@hidden>
> >
> > The constraint for `rdinstreth` was comparing the csr number to 0xc80,
> > which is `cycleh` instead. Fix this.
> >
> > Author: Wladimir J. van der Laan <address@hidden>
>
> I'm not sure what this tag is supposed to mean. If this is the actual author
> of the patch, then shouldn't it also have a SOB?
I'm not sure either, that is the line that the patch had and I didn't
want to change it. I'm not sure what usually happens in cases like
this.
Alistair
>
> > Signed-off-by: Michael Clark <address@hidden>
> > Signed-off-by: Alistair Francis <address@hidden>
> > ---
> > disas/riscv.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/disas/riscv.c b/disas/riscv.c
> > index 3ab4586f0a..c2578a3c4b 100644
> > --- a/disas/riscv.c
> > +++ b/disas/riscv.c
> > @@ -614,7 +614,7 @@ static const rvc_constraint rvcc_rdtime[] = {
> > rvc_rs1_eq_x0, rvc_csr_eq_0xc01, r
> > static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
> > rvc_csr_eq_0xc02, rvc_end };
> > static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
> > rvc_csr_eq_0xc80, rvc_end };
> > static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0,
> > rvc_csr_eq_0xc81, rvc_end };
> > -static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
> > rvc_csr_eq_0xc80, rvc_end };
> > +static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
> > rvc_csr_eq_0xc82, rvc_end };
> > static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0,
> > rvc_csr_eq_0x003, rvc_end };
> > static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0,
> > rvc_csr_eq_0x002, rvc_end };
> > static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0,
> > rvc_csr_eq_0x001, rvc_end };