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Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use
From: |
Alistair Francis |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead |
Date: |
Fri, 23 Aug 2019 10:38:57 -0700 |
On Thu, Aug 22, 2019 at 10:21 PM Bin Meng <address@hidden> wrote:
>
> Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
> in various sifive models.
>
> Signed-off-by: Bin Meng <address@hidden>
Thanks for this cleanup!
Reviewed-by: Alistair Francis <address@hidden>
Alistair
>
> ---
>
> Changes in v5:
> - new patch to change to use qemu_log_mask(LOG_GUEST_ERROR,...) instead
> in various sifive models
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> hw/riscv/sifive_prci.c | 8 +++++---
> hw/riscv/sifive_test.c | 5 +++--
> hw/riscv/sifive_uart.c | 9 +++++----
> 3 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
> index f406682..1ab98d4 100644
> --- a/hw/riscv/sifive_prci.c
> +++ b/hw/riscv/sifive_prci.c
> @@ -20,6 +20,7 @@
>
> #include "qemu/osdep.h"
> #include "hw/sysbus.h"
> +#include "qemu/log.h"
> #include "qemu/module.h"
> #include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_prci.h"
> @@ -37,7 +38,8 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr,
> unsigned int size)
> case SIFIVE_PRCI_PLLOUTDIV:
> return s->plloutdiv;
> }
> - hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
> + __func__, (int)addr);
> return 0;
> }
>
> @@ -65,8 +67,8 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
> s->plloutdiv = (uint32_t) val64;
> break;
> default:
> - hw_error("%s: bad write: addr=0x%x v=0x%x\n",
> - __func__, (int)addr, (int)val64);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
> + __func__, (int)addr, (int)val64);
> }
> }
>
> diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
> index cd86831..655a3d7 100644
> --- a/hw/riscv/sifive_test.c
> +++ b/hw/riscv/sifive_test.c
> @@ -20,6 +20,7 @@
>
> #include "qemu/osdep.h"
> #include "hw/sysbus.h"
> +#include "qemu/log.h"
> #include "qemu/module.h"
> #include "sysemu/sysemu.h"
> #include "target/riscv/cpu.h"
> @@ -48,8 +49,8 @@ static void sifive_test_write(void *opaque, hwaddr addr,
> break;
> }
> }
> - hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
> - __func__, (int)addr, val64);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64
> "\n",
> + __func__, (int)addr, val64);
> }
>
> static const MemoryRegionOps sifive_test_ops = {
> diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
> index 3b3f94f..cd74043 100644
> --- a/hw/riscv/sifive_uart.c
> +++ b/hw/riscv/sifive_uart.c
> @@ -18,6 +18,7 @@
>
> #include "qemu/osdep.h"
> #include "qapi/error.h"
> +#include "qemu/log.h"
> #include "hw/sysbus.h"
> #include "chardev/char.h"
> #include "chardev/char-fe.h"
> @@ -93,8 +94,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
> return s->div;
> }
>
> - hw_error("%s: bad read: addr=0x%x\n",
> - __func__, (int)addr);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n",
> + __func__, (int)addr);
> return 0;
> }
>
> @@ -125,8 +126,8 @@ uart_write(void *opaque, hwaddr addr,
> s->div = val64;
> return;
> }
> - hw_error("%s: bad write: addr=0x%x v=0x%x\n",
> - __func__, (int)addr, (int)value);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
> + __func__, (int)addr, (int)value);
> }
>
> static const MemoryRegionOps uart_ops = {
> --
> 2.7.4
>
>
- [Qemu-riscv] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Bin Meng, 2019/08/23
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead,
Alistair Francis <=
- [Qemu-riscv] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/23