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[PATCH v1 21/36] target/ricsv: Flush the TLB on virtulisation mode chang
From: |
Alistair Francis |
Subject: |
[PATCH v1 21/36] target/ricsv: Flush the TLB on virtulisation mode changes |
Date: |
Mon, 9 Dec 2019 10:11:35 -0800 |
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 85eed5d885..1b747abf93 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -183,6 +183,11 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
return;
}
+ /* Flush the TLB on all virt mode changes. */
+ if (get_field(env->virt, VIRT_ONOFF) != enable) {
+ tlb_flush(env_cpu(env));
+ }
+
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
}
--
2.24.0
- [PATCH v1 11/36] target/riscv: Dump Hypervisor registers if enabled, (continued)
- [PATCH v1 11/36] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/12/09
- [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/12/09
- [PATCH v1 13/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 16/36] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/12/09
- [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2019/12/09
- [PATCH v1 15/36] target/riscv: Convert mstatus to pointers, Alistair Francis, 2019/12/09
- [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/12/09
- [PATCH v1 21/36] target/ricsv: Flush the TLB on virtulisation mode changes,
Alistair Francis <=
- [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/12/09
- [PATCH v1 23/36] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/12/09
- [PATCH v1 24/36] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/12/09
- [PATCH v1 25/36] target/riscv: Add hfence instructions, Alistair Francis, 2019/12/09
- [PATCH v1 26/36] target/riscv: Remove the hret instruction, Alistair Francis, 2019/12/09
- [PATCH v1 28/36] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/12/09
- [PATCH v1 27/36] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/12/09
- [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/12/09
- [PATCH v1 30/36] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/12/09
- [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails, Alistair Francis, 2019/12/09