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[PATCH 1/3] select gdb fpu xml by single or double float extension
From: |
LIU Zhiwei |
Subject: |
[PATCH 1/3] select gdb fpu xml by single or double float extension |
Date: |
Fri, 10 Jan 2020 16:12:18 +0800 |
There is no reason why RISCV32 can't use RVD extension,
or RISCV64 can't just use RVF extension. And gdb will check
flen according to RVD or RVF feature in elf header.
Signed-off-by: LIU Zhiwei <address@hidden>
---
configure | 4 ++--
target/riscv/gdbstub.c | 14 ++++++--------
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/configure b/configure
index 0ce2c0354a..2757c0a5a5 100755
--- a/configure
+++ b/configure
@@ -7679,13 +7679,13 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml
riscv-32bit-virtual.xml"
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml
riscv-32bit-csr.xml riscv-32bit-virtual.xml"
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml
riscv-64bit-virtual.xml"
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml
riscv-64bit-csr.xml riscv-64bit-virtual.xml"
;;
sh4|sh4eb)
TARGET_ARCH=sh4
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 1a7947e019..e3c9b320fb 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -403,23 +403,21 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-#if defined(TARGET_RISCV32)
- if (env->misa & RVF) {
+ if (env->misa & RVD) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 36, "riscv-64bit-fpu.xml", 0);
+ } else if (env->misa & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-32bit-fpu.xml", 0);
+ 36, "riscv-32bit-fpu.xml", 0);
}
+#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-32bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
#elif defined(TARGET_RISCV64)
- if (env->misa & RVF) {
- gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-64bit-fpu.xml", 0);
- }
-
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-64bit-csr.xml", 0);
--
2.23.0
- [PATCH 1/3] select gdb fpu xml by single or double float extension,
LIU Zhiwei <=