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[PULL 2/5] riscv: Set xPIE to 1 after xRET
From: |
Palmer Dabbelt |
Subject: |
[PULL 2/5] riscv: Set xPIE to 1 after xRET |
Date: |
Tue, 21 Jan 2020 14:56:59 -0800 |
From: Yiting Wang <address@hidden>
When executing an xRET instruction, supposing xPP holds the
value y, xIE is set to xPIE; the privilege mode is changed to y;
xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.
Signed-off-by: Yiting Wang <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 331cc36232..e87c9115bc 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -93,7 +93,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong
cpu_pc_deb)
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_SIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_SPIE));
- mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
+ mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
@@ -118,7 +118,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_MPIE));
- mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
+ mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
--
2.25.0.341.g760bfbb309-goog
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1, Palmer Dabbelt, 2020/01/21
- [PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize(), Palmer Dabbelt, 2020/01/21
- [PULL 3/5] target/riscv: Fix tb->flags FS status, Palmer Dabbelt, 2020/01/21
- [PULL 2/5] riscv: Set xPIE to 1 after xRET,
Palmer Dabbelt <=
- [PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state, Palmer Dabbelt, 2020/01/21
- [PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty, Palmer Dabbelt, 2020/01/21
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1, Peter Maydell, 2020/01/23
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1, Palmer Dabbelt, 2020/01/23
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1, Peter Maydell, 2020/01/24