Re: [PATCH v1 1/1] target/riscv: Correctly implement TSR trap

[Palmer Dabbelt]

On Thu, 20 Feb 2020 10:41:35 PST (-0800), address@hidden wrote:
> On Mon, Jan 20, 2020 at 9:43 PM Alistair Francis
> <address@hidden> wrote:
> > As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
> > correctly handling illegal instructions based on the value of MSTATUS_TSR
> > and the current privledge level.
> >
> > This patch fixes the issue raised in the bug by raising an illegal
> > instruction if TSR is set and we are in S-Mode.
> >
> > Signed-off-by: Alistair Francis <address@hidden>
>
> @Palmer Dabbelt  Ping!

Sorry, I must have missed this.  It's in the queue (with the reviews as
collected by patchwork).

Thanks!

> Alistair
>
> > ---
> >  target/riscv/op_helper.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> > index 331cc36232..eed8eea6f2 100644
> > --- a/target/riscv/op_helper.c
> > +++ b/target/riscv/op_helper.c
> > @@ -83,7 +83,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong 
> > cpu_pc_deb)
> >      }
> >
> >      if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
> > -        get_field(env->mstatus, MSTATUS_TSR)) {
> > +        get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
> >          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >      }
> >
> > --
> > 2.24.1