Re: [PATCH RFC 0/9] Add riscv64 kvm accel support

[Anup Patel]

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <address@hidden> wrote:
>
> Hi,
>
> This series adds riscv64 kvm support, It is based on riscv_kvm_master
> branch at https://github.com/kvm-riscv/linux.
>
> This series depends on above pending changes which haven't yet been
> accepted, so this QEMU patch series is blocked until that dependency
> has been dealt with, but is worth reviewing anyway.
>
> Several steps to use this:
>
> 1. Build riscv64 emulation
> $ ./configure --target-list=riscv64-softmmu
> $ make -j$(nproc)
>
> 2. Build kernel
> riscv_kvm_master branch at https://github.com/kvm-riscv/linux
>
> 3. Build QEMU VM
> I cross build in riscv toolchain
> $ PKG_CONFIG_LIBDIR=<toolchain pkgconfig path>
> $ export PKG_CONFIG_SYSROOT_DIR=<toolchain sysroot path>
> $ ./configure --target-list=riscv64-softmmu --enable-kvm \
> --cross-prefix=riscv64-linux-gnu- --disable-libiscsi --disable-glusterfs \
> --disable-libusb --disable-usb-redir --audio-drv-list= --disable-opengl \
> --disable-libxml2
>
> 4. Start riscv64 emulation
> $ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
>         -name guest=riscv-hyp,debug-threads=on \
>         -smp 4 \
>         -kernel ./fw_jump.elf \
>         -device loader,file=./Image,addr=0x80200000 \
>         -drive file=./hyp.img,format=raw,id=hd0 \
>         -device virtio-blk-device,drive=hd0 \
>         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> 5. Start kvm-acceled QEMU VM in riscv64 emulation
> $ ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \
>         -name guest=riscv-guset \
>          -smp 2 \
>         -kernel ./Image \
>         -drive file=./guest.img,format=raw,id=hd0 \
>         -device virtio-blk-device,drive=hd0 \
>         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> Yifei Jiang (9):
>   linux-header: Update linux/kvm.h
>   target/riscv: Add target/riscv/kvm.c to place the public kvm interface
>   target/riscv: Implement function kvm_arch_init_vcpu
>   target/riscv: Implement kvm_arch_get_registers
>   target/riscv: Implement kvm_arch_put_registers
>   target/riscv: Support start kernel directly by KVM
>   hw/riscv: PLIC update external interrupt by KVM when kvm enabled
>   target/riscv: Handler KVM_EXIT_RISCV_SBI exit
>   target/riscv: add host riscv64 cpu type
>
>  configure                  |   1 +
>  hw/riscv/sifive_plic.c     |  31 ++-
>  hw/riscv/virt.c            |  15 +-
>  linux-headers/linux/kvm.h  |   8 +
>  target/riscv/Makefile.objs |   1 +
>  target/riscv/cpu.c         |   9 +
>  target/riscv/cpu.h         |   4 +
>  target/riscv/kvm.c         | 513 +++++++++++++++++++++++++++++++++++++
>  target/riscv/kvm_riscv.h   |  25 ++
>  9 files changed, 596 insertions(+), 11 deletions(-)
>  create mode 100644 target/riscv/kvm.c
>  create mode 100644 target/riscv/kvm_riscv.h
>
> --
> 2.19.1
>
>
>

First of all many thanks for doing QEMU KVM support. It wasted
bit of my time because I was already doing it but I am happy to
see the patches on list sooner.

In future, please CC the KVM RISC-V mailing list for all QEMU KVM
RISC-V work. The KVM RISC-V mailing list for related projects
(QEMU, KVMTOOL, libvirt, etc) and not just Linux KVM RISC-V.

Currently, we can only review this patch series and get it in final
shape but it can only be merged in QEMU after Linux KVM RISC-V
patches are merged in Linux kernel.

I will be sending out KVM RISC-V v11 series today. There is
a crucial bug fix related to HIDELEG CSR programing. This
bug fix is required in both QEMU and KVM RISC-V. Palmer has
already accepted QEMU HIDELEG CSR fix. The KVM RISC-V
v11 series will have this fix as well.

Thanks & Regards,
Anup Patel