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Re: [PATCH v5 50/60] target/riscv: vmfirst find-first-set mask bit
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v5 50/60] target/riscv: vmfirst find-first-set mask bit |
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Date: |
Sat, 14 Mar 2020 18:36:50 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* vmfirst find-first-set mask bit*/
> +target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
> + uint32_t desc)
> +{
> + uint32_t mlen = vext_mlen(desc);
> + uint32_t vm = vext_vm(desc);
> + uint32_t vl = env->vl;
> + int i;
> +
> + for (i = 0; i < vl; i++) {
> + if (vm || vext_elem_mask(v0, mlen, i)) {
> + if (vext_elem_mask(vs2, mlen, i)) {
> + return i;
> + }
> + }
> + }
> + return -1LL;
> +}
This is ok as-is, so
Reviewed-by: Richard Henderson <address@hidden>
But you can do better. With the mask, as discussed, the inner loop looks like
j = mask;
j &= ((uint64_t *)vs2)[i];
j &= ((uint64_t *)v0)[i];
if (j) {
k = ctz64(j) + i * 64;
return k >> log2_mlen;
}
r~
- [PATCH v5 45/60] target/riscv: vector wideing integer reduction instructions, (continued)
- [PATCH v5 45/60] target/riscv: vector wideing integer reduction instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 46/60] target/riscv: vector single-width floating-point reduction instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 47/60] target/riscv: vector widening floating-point reduction instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 48/60] target/riscv: vector mask-register logical instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 49/60] target/riscv: vector mask population count vmpopc, LIU Zhiwei, 2020/03/12
- [PATCH v5 50/60] target/riscv: vmfirst find-first-set mask bit, LIU Zhiwei, 2020/03/12
- Re: [PATCH v5 50/60] target/riscv: vmfirst find-first-set mask bit,
Richard Henderson <=
- [PATCH v5 51/60] target/riscv: set-X-first mask bit, LIU Zhiwei, 2020/03/12
- [PATCH v5 52/60] target/riscv: vector iota instruction, LIU Zhiwei, 2020/03/12
- [PATCH v5 53/60] target/riscv: vector element index instruction, LIU Zhiwei, 2020/03/12
- [PATCH v5 54/60] target/riscv: integer extract instruction, LIU Zhiwei, 2020/03/12
- [PATCH v5 55/60] target/riscv: integer scalar move instruction, LIU Zhiwei, 2020/03/12