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[PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit
From: |
Palmer Dabbelt |
Subject: |
[PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit |
Date: |
Mon, 16 Mar 2020 21:05:45 -0700 |
From: Bin Meng <address@hidden>
Update BIOS_FILENAME to consider 32-bit bios image file name.
Tested booting Linux v5.5 32-bit image (built from rv32_defconfig
plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 156a003642..4409ea1ccc 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -56,7 +56,11 @@
#include <libfdt.h>
-#define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
+#if defined(TARGET_RISCV32)
+# define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin"
+#else
+# define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
+#endif
static const struct MemmapEntry {
hwaddr base;
--
2.25.1.481.gfbce0eb801-goog
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5, Palmer Dabbelt, 2020/03/17
- [PULL 1/6] target/riscv: Correctly implement TSR trap, Palmer Dabbelt, 2020/03/17
- [PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit,
Palmer Dabbelt <=
- [PULL 6/6] target/riscv: Fix VS mode interrupts forwarding., Palmer Dabbelt, 2020/03/17
- [PULL 5/6] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries, Palmer Dabbelt, 2020/03/17
- [PULL 3/6] roms: opensbi: Add 32-bit firmware image for sifive_u machine, Palmer Dabbelt, 2020/03/17
- [PULL 2/6] roms: opensbi: Upgrade from v0.5 to v0.6, Palmer Dabbelt, 2020/03/17
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5, Peter Maydell, 2020/03/17