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Re: [PATCH v6 05/61] target/riscv: add an internals.h header
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v6 05/61] target/riscv: add an internals.h header |
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Date: |
Wed, 18 Mar 2020 16:45:46 -0700 |
On Tue, Mar 17, 2020 at 8:17 AM LIU Zhiwei <address@hidden> wrote:
>
> The internals.h keeps things that are not relevant to the actual architecture,
> only to the implementation, separate.
>
> Signed-off-by: LIU Zhiwei <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> target/riscv/internals.h | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 target/riscv/internals.h
>
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> new file mode 100644
> index 0000000000..cabea18e1d
> --- /dev/null
> +++ b/target/riscv/internals.h
> @@ -0,0 +1,24 @@
> +/*
> + * QEMU RISC-V CPU -- internal functions and types
> + *
> + * Copyright (c) 2020 C-SKY Limited. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef RISCV_CPU_INTERNALS_H
> +#define RISCV_CPU_INTERNALS_H
> +
> +#include "hw/registerfields.h"
> +
> +#endif
> --
> 2.23.0
>
- [PATCH v6 00/61] target/riscv: support vector extension v0.7.1, LIU Zhiwei, 2020/03/17
- [PATCH v6 01/61] target/riscv: add vector extension field in CPURISCVState, LIU Zhiwei, 2020/03/17
- [PATCH v6 02/61] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2020/03/17
- [PATCH v6 03/61] target/riscv: support vector extension csr, LIU Zhiwei, 2020/03/17
- [PATCH v6 04/61] target/riscv: add vector configure instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 05/61] target/riscv: add an internals.h header, LIU Zhiwei, 2020/03/17
- [PATCH v6 06/61] target/riscv: add vector stride load and store instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 07/61] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 08/61] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/03/17
- [PATCH v6 09/61] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/17
- [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/17