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Re: [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs |
Date: |
Mon, 27 Apr 2020 08:00:14 -0700 |
On Mon, Apr 27, 2020 at 1:09 AM Anup Patel <address@hidden> wrote:
>
> Currently, the upstream Spike ISA simulator allows more than
> one CPUs so we update QEMU Spike machine on similar lines to
> allow more than one CPUs.
>
> The maximum number of CPUs for QEMU Spike machine is kept
> same as QEMU Virt machine.
>
> Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> hw/riscv/spike.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index b0395e227c..1799b9291c 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -472,7 +472,7 @@ static void spike_machine_init(MachineClass *mc)
> {
> mc->desc = "RISC-V Spike Board";
> mc->init = spike_board_init;
> - mc->max_cpus = 1;
> + mc->max_cpus = 8;
> mc->is_default = true;
> mc->default_cpu_type = SPIKE_V1_10_0_CPU;
> }
> --
> 2.25.1
>
>