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Re: [PULL 00/14] RISC-V Patch Queue for 5.1
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 00/14] RISC-V Patch Queue for 5.1 |
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Date: |
Wed, 29 Apr 2020 21:03:56 +0100 |
On Wed, 29 Apr 2020 at 19:37, Alistair Francis <address@hidden> wrote:
>
> The following changes since commit a7922a3c81f34f45b1ebc9670a7769edc4c42a43:
>
> Open 5.1 development tree (2020-04-29 15:07:10 +0100)
>
> are available in the Git repository at:
>
> address@hidden:alistair23/qemu.git tags/pull-riscv-to-apply-20200429-1
>
> for you to fetch changes up to 23766b6a35d5b1664ab782c02624bf2435c4ed5d:
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> hw/riscv/spike: Allow more than one CPUs (2020-04-29 11:23:44 -0700)
>
> ----------------------------------------------------------------
> RISC-V pull request for 5.1
>
> This is the first pull request for the 5.1 development period. It
> contains all of the patches that were sent during the 5.0 timeframe.
>
> This is an assortment of fixes for RISC-V, including fixes for the
> Hypervisor extension, the Spike machine and an update to OpenSBI.
>
> --------------------------------------------------------------
Hi; this doesn't apply to current master. The conflict looks like
it's probably pretty easy to fix up, but could you fix it and resend,
please?
thanks
-- PMM
- [PULL 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, (continued)
- [PULL 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/04/29
- [PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags, Alistair Francis, 2020/04/29
- [PULL 10/14] linux-user/riscv: fix up struct target_ucontext definition, Alistair Francis, 2020/04/29
- [PULL 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines, Alistair Francis, 2020/04/29
- [PULL 08/14] riscv: sifive_e: Support changing CPU type, Alistair Francis, 2020/04/29
- [PULL 09/14] target/riscv: Add a sifive-e34 cpu type, Alistair Francis, 2020/04/29
- [PULL 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware(), Alistair Francis, 2020/04/29
- [PULL 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option, Alistair Francis, 2020/04/29
- [PULL 14/14] hw/riscv/spike: Allow more than one CPUs, Alistair Francis, 2020/04/29
- [PULL 11/14] roms: opensbi: Upgrade from v0.6 to v0.7, Alistair Francis, 2020/04/29
- Re: [PULL 00/14] RISC-V Patch Queue for 5.1,
Peter Maydell <=