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[RFC PATCH 0/8] RISCV risu porting
From: |
LIU Zhiwei |
Subject: |
[RFC PATCH 0/8] RISCV risu porting |
Date: |
Thu, 30 Apr 2020 15:21:31 +0800 |
When I test RISCV vector extension, many folks advice risu. Here is a
very simple port only support RV64I, RV64F, RV64M.
It's some difficult when I try to support RV32, because it's very
similiar to RV64, so I can't make two .risu files like arm.risu and
aarch64.risu.
Any idea are welcomed.
LIU Zhiwei (8):
riscv: Add RV64I instructions description
riscv: Generate payload scripts
riscv: Define riscv struct reginfo
riscv: Implement payload load interfaces
riscv: Add standard test case
riscv: Add configure script
riscv: Add RV64M instructions description
riscv: Add RV64F instructions description
configure | 4 +-
riscv64.risu | 262 +++++++++++++++++++++
risu_reginfo_riscv64.c | 134 +++++++++++
risu_reginfo_riscv64.h | 29 +++
risu_riscv64.c | 47 ++++
risugen_riscv.pm | 501 +++++++++++++++++++++++++++++++++++++++++
test_riscv64.s | 85 +++++++
7 files changed, 1061 insertions(+), 1 deletion(-)
create mode 100644 riscv64.risu
create mode 100644 risu_reginfo_riscv64.c
create mode 100644 risu_reginfo_riscv64.h
create mode 100644 risu_riscv64.c
create mode 100644 risugen_riscv.pm
create mode 100644 test_riscv64.s
--
2.23.0
- [RFC PATCH 0/8] RISCV risu porting,
LIU Zhiwei <=
- [RFC PATCH 5/8] riscv: Add standard test case, LIU Zhiwei, 2020/04/30
- [RFC PATCH 6/8] riscv: Add configure script, LIU Zhiwei, 2020/04/30
- [RFC PATCH 3/8] riscv: Define riscv struct reginfo, LIU Zhiwei, 2020/04/30
- [RFC PATCH 7/8] riscv: Add RV64M instructions description, LIU Zhiwei, 2020/04/30
- [RFC PATCH 1/8] riscv: Add RV64I instructions description, LIU Zhiwei, 2020/04/30
- [RFC PATCH 8/8] riscv: Add RV64F instructions description, LIU Zhiwei, 2020/04/30
- [RFC PATCH 4/8] riscv: Implement payload load interfaces, LIU Zhiwei, 2020/04/30
- [RFC PATCH 2/8] riscv: Generate payload scripts, LIU Zhiwei, 2020/04/30