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Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs |
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Date: |
Mon, 1 Jun 2020 14:22:10 -0700 |
On Sun, May 31, 2020 at 9:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, May 29, 2020 at 6:24 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Bin Meng <bin.meng@windriver.com>
> > ---
> > docs/system/deprecated.rst | 33 ++++++++++++++++++---------------
> > target/riscv/cpu.h | 7 -------
> > target/riscv/cpu.c | 28 ----------------------------
> > tests/qtest/machine-none-test.c | 4 ++--
> > 4 files changed, 20 insertions(+), 52 deletions(-)
> >
> > diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
> > index 50927bad74..a6664bfca9 100644
> > --- a/docs/system/deprecated.rst
> > +++ b/docs/system/deprecated.rst
> > @@ -314,21 +314,6 @@ should be used instead of the 1.09.1 version.
> > System emulator CPUS
> > --------------------
> >
> > -RISC-V ISA CPUs (since 4.1)
> > -'''''''''''''''''''''''''''
> > -
> > -The RISC-V cpus with the ISA version in the CPU name have been depcreated.
> > The
> > -four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``,
> > ``rv64gcsu-v1.9.1`` and
> > -``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU
> > ``priv_spec``
> > -option when using the ``rv32`` or ``rv64`` CPUs.
> > -
> > -RISC-V ISA CPUs (since 4.1)
>
> Not sure if this is a typo. Should we say: RISC-V no MMU CPUs ? If
> not, since the subsection titles are the same, should we merge the
> following description to above?
Good point.
To be more clear I have changed this to:
RISC-V ISA Specific CPUs (removed in 5.1)
...
RISC-V no MMU CPUs (removed in 5.1)
>
> > -'''''''''''''''''''''''''''
> > -
> > -The RISC-V no MMU cpus have been depcreated. The two CPUs:
> > ``rv32imacu-nommu`` and
> > -``rv64imacu-nommu`` should no longer be used. Instead the MMU status can
> > be specified
> > -via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> > -
> > ``compat`` property of server class POWER CPUs (since 5.0)
> > ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
> >
> > @@ -486,6 +471,24 @@ The ``hub_id`` parameter of ``hostfwd_add`` /
> > ``hostfwd_remove`` (removed in 5.0
> > The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
> > 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
> >
> > +System emulator CPUS
> > +--------------------
> > +
> > +RISC-V ISA CPUs (removed in 5.1)
> > +''''''''''''''''''''''''''''''''
> > +
> > +The RISC-V cpus with the ISA version in the CPU name have been removed. The
> > +four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``,
> > ``rv64gcsu-v1.9.1`` and
> > +``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU
> > ``priv_spec``
> > +option when using the ``rv32`` or ``rv64`` CPUs.
> > +
> > +RISC-V ISA CPUs (removed in 5.1)
> > +''''''''''''''''''''''''''''''''
> > +
> > +The RISC-V no MMU cpus have been removed. The two CPUs:
> > ``rv32imacu-nommu`` and
> > +``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be
> > specified
> > +via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> > +
> > System emulator machines
> > ------------------------
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index d0e7f5b9c5..76b98d7a33 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -40,13 +40,6 @@
> > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> > -/* Deprecated */
> > -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU
> > RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1
> > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0
> > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> > -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU
> > RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1
> > RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0
> > RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
> >
> > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
> > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 059d71f2c7..112f2e3a2f 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
> > set_misa(env, 0);
> > }
> >
> > -static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
> > -{
> > - CPURISCVState *env = &RISCV_CPU(obj)->env;
> > - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > - set_priv_version(env, PRIV_VERSION_1_09_1);
> > - set_resetvec(env, DEFAULT_RSTVEC);
> > - set_feature(env, RISCV_FEATURE_MMU);
> > - set_feature(env, RISCV_FEATURE_PMP);
> > -}
> > -
> > static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > @@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
> > set_misa(env, 0);
> > }
> >
> > -static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
> > -{
> > - CPURISCVState *env = &RISCV_CPU(obj)->env;
> > - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > - set_priv_version(env, PRIV_VERSION_1_09_1);
> > - set_resetvec(env, DEFAULT_RSTVEC);
> > - set_feature(env, RISCV_FEATURE_MMU);
> > - set_feature(env, RISCV_FEATURE_PMP);
> > -}
> > -
> > static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > @@ -621,18 +601,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,
> > rv32gcsu_priv1_10_0_cpu_init),
> > - /* Depreacted */
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1,
> > rv32gcsu_priv1_09_1_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0,
> > rv32gcsu_priv1_10_0_cpu_init)
> > #elif defined(TARGET_RISCV64)
> > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,
> > rv64gcsu_priv1_10_0_cpu_init),
> > - /* Deprecated */
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1,
> > rv64gcsu_priv1_09_1_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0,
> > rv64gcsu_priv1_10_0_cpu_init)
> > #endif
> > };
> >
> > diff --git a/tests/qtest/machine-none-test.c
> > b/tests/qtest/machine-none-test.c
> > index 8bb54a6360..b52311ec2e 100644
> > --- a/tests/qtest/machine-none-test.c
> > +++ b/tests/qtest/machine-none-test.c
> > @@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] = {
> > { "xtensa", "dc233c" },
> > { "xtensaeb", "fsf" },
> > { "hppa", "hppa" },
> > - { "riscv64", "rv64gcsu-v1.10.0" },
> > - { "riscv32", "rv32gcsu-v1.9.1" },
> > + { "riscv64", "sifive-u54" },
> > + { "riscv32", "sifive-u34" },
>
> I believe we should use "rv32" and "rv64" here.
Done.
Alistair
>
> > { "rx", "rx62n" },
> > };
>
> Regards,
> Bin