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[PATCH v2 13/17] target/riscv: Only support a single VSXL length
From: |
Alistair Francis |
Subject: |
[PATCH v2 13/17] target/riscv: Only support a single VSXL length |
Date: |
Thu, 4 Jun 2020 18:21:18 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 69a3c8379c..973404d0aa 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -768,12 +768,21 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->hstatus;
+#ifdef TARGET_RISCV64
+ /* We only support 64-bit VSXL */
+ *val = set_field(*val, HSTATUS_VSXL, 2);
+#endif
return 0;
}
static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
{
env->hstatus = val;
+#ifdef TARGET_RISCV64
+ if (get_field(val, HSTATUS_VSXL) != 2) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN
options.");
+ }
+#endif
return 0;
}
--
2.26.2
- Re: [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode, (continued)
- [PATCH v2 04/17] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/04
- [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/06/04
- [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/06/04
- [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/06/04
- [PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/06/04
- [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/06/04
- [PATCH v2 13/17] target/riscv: Only support a single VSXL length,
Alistair Francis <=
- [PATCH v2 10/17] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/06/04
- [PATCH v2 14/17] target/riscv: Only support little endian guests, Alistair Francis, 2020/06/04
- [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/06/04
- [PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/06/04
- [PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/06/04