Re: [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support

[Alistair Francis]

On Mon, Jun 8, 2020 at 7:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This series updates the 'sifive_u' machine support:
>
> - Add GPIO controller support
> - Support reboot functionality via GPIO pin#10
> - Change SiFive E/U series CPU reset vector to 0x1004
> - Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new
>   "msel" machine property
> - Add a dummy DDR memory controller device
>
> The series also does some clean-ups to the existing codes.
>
> With this series, QEMU can boot U-Boot SPL built for SiFive FU540
> all the way up to loading U-Boot proper from MMC:
>
> $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
>
> U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
> Trying to boot from MMC1
> Unhandled exception: Load access fault
> EPC: 0000000008009be6 TVAL: 0000000010050014
>
> The last big gap for the 'sifive_u' machine is the QSPI modeling.
>
>
> Bin Meng (15):
>   hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc*
>     functions
>   hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc*
>     functions
>   hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
>   hw/riscv: sifive_u: Generate device tree node for OTP
>   hw/riscv: sifive_gpio: Clean up the codes
>   hw/riscv: sifive_gpio: Add a new 'ngpio' property
>   hw/riscv: sifive_u: Hook a GPIO controller
>   hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
>   hw/riscv: sifive_u: Add reset functionality
>   hw/riscv: sifive_u: Rename serial property get/set functions to a
>     generic name
>   hw/riscv: sifive_u: Add a new property msel for MSEL pin state
>   hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
>   hw/riscv: sifive_u: Support different boot source per MSEL pin state
>   hw/riscv: sifive_u: Sort the SoC memmap table entries
>   hw/riscv: sifive_u: Add a dummy DDR memory controller device

I have applied patches 1 to 11 to the RISC-V branch.

Alistair

>
>  hw/riscv/opentitan.c           |  29 ++++----
>  hw/riscv/sifive_e.c            |  32 +++++----
>  hw/riscv/sifive_gpio.c         |  45 +++++++-----
>  hw/riscv/sifive_u.c            | 158 
> ++++++++++++++++++++++++++++++++++-------
>  include/hw/riscv/sifive_gpio.h |   8 ++-
>  include/hw/riscv/sifive_u.h    |  27 +++++++
>  target/riscv/cpu.c             |   4 +-
>  7 files changed, 223 insertions(+), 80 deletions(-)
>
> --
> 2.7.4
>
>