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Re: [PATCH v12 00/61] target/riscv: support vector extension v0.7.1
From: |
Alistair Francis |
Subject: |
Re: [PATCH v12 00/61] target/riscv: support vector extension v0.7.1 |
Date: |
Wed, 1 Jul 2020 20:32:00 -0700 |
On Wed, Jul 1, 2020 at 8:26 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> This patchset implements the vector extension for RISC-V on QEMU.
>
> You can also find the patchset and all *test cases* in
> my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v12).
> All the test cases are in the directory qemu/tests/riscv/vector/. They are
> riscv64 linux user mode programs.
>
> You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.
>
> Features:
> * support specification
> riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
> * support basic vector extension.
> * support Zvlsseg.
> * support Zvamo.
> * not support Zvediv as it is changing.
> * SLEN always equals VLEN.
> * element width support 8bit, 16bit, 32bit, 64bit.
>
> Changelog:
>
> v12
> * fix compile error on big endian machines.
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> v11
> * fix all non-ASCII characters.
>
> v10
> * rebase to https://github.com/alistair23/qemu/tree/riscv-to-apply.next.
> * fix compile error in patch 57/61.
> * fix review tag typo.
>
> v9
> * always set dynamic rounding mode for vector float insns.
> * bug fix atomic implementation.
> * bug fix first-only-fault.
> * some small tidy up.
>
> v8
> * support different float rounding modes for vector instructions.
> * use lastest released TCG GVEC DUP IR.
> * set RV_VLEN_MAX to 256 bits, as GVEC IR uses simd_desc.
>
> v7
> * move vl == 0 check to translation time by add a global cpu_vl.
> * implement vector element inline load and store function by TCG IR.
> * based on vec_element_load(store), implement some permutation instructions.
> * implement rsubs GVEC IR.
> * fixup vsmul, vmfne, vfmerge, vslidedown.
> * some other small bugs and indentation errors.
>
> v6
> * use gvec_dup Gvec IR to accellerate move and merge.
> * a better way to implement fixed point instructions.
> * a global check when vl == 0.
> * limit some macros to only one inline function call.
> * fixup sew error when use Gvec IR.
> * fixup bugs for corner cases.
>
> v5
> * fixup a bug in tb flags.
>
> v4
> * no change
>
> v3
> * move check code from execution-time to translation-time
> * use a continous memory block for vector register description.
> * vector registers as direct fields in RISCVCPUState.
> * support VLEN configure from qemu command line.
> * support ELEN configure from qemu command line.
> * support vector specification version configure from qemu command line.
> * probe pages before real load or store access.
> * use probe_page_check for no-fault operations in linux user mode.
> * generation atomic exit exception when in parallel environment.
> * fixup a lot of concrete bugs.
>
> V2
> * use float16_compare{_quiet}
> * only use GETPC() in outer most helper
> * add ctx.ext_v Property
>
>
> LIU Zhiwei (61):
> target/riscv: add vector extension field in CPURISCVState
> target/riscv: implementation-defined constant parameters
> target/riscv: support vector extension csr
> target/riscv: add vector configure instruction
> target/riscv: add an internals.h header
> target/riscv: add vector stride load and store instructions
> target/riscv: add vector index load and store instructions
> target/riscv: add fault-only-first unit stride load
> target/riscv: add vector amo operations
> target/riscv: vector single-width integer add and subtract
> target/riscv: vector widening integer add and subtract
> target/riscv: vector integer add-with-carry / subtract-with-borrow
> instructions
> target/riscv: vector bitwise logical instructions
> target/riscv: vector single-width bit shift instructions
> target/riscv: vector narrowing integer right shift instructions
> target/riscv: vector integer comparison instructions
> target/riscv: vector integer min/max instructions
> target/riscv: vector single-width integer multiply instructions
> target/riscv: vector integer divide instructions
> target/riscv: vector widening integer multiply instructions
> target/riscv: vector single-width integer multiply-add instructions
> target/riscv: vector widening integer multiply-add instructions
> target/riscv: vector integer merge and move instructions
> target/riscv: vector single-width saturating add and subtract
> target/riscv: vector single-width averaging add and subtract
> target/riscv: vector single-width fractional multiply with rounding
> and saturation
> target/riscv: vector widening saturating scaled multiply-add
> target/riscv: vector single-width scaling shift instructions
> target/riscv: vector narrowing fixed-point clip instructions
> target/riscv: vector single-width floating-point add/subtract
> instructions
> target/riscv: vector widening floating-point add/subtract instructions
> target/riscv: vector single-width floating-point multiply/divide
> instructions
> target/riscv: vector widening floating-point multiply
> target/riscv: vector single-width floating-point fused multiply-add
> instructions
> target/riscv: vector widening floating-point fused multiply-add
> instructions
> target/riscv: vector floating-point square-root instruction
> target/riscv: vector floating-point min/max instructions
> target/riscv: vector floating-point sign-injection instructions
> target/riscv: vector floating-point compare instructions
> target/riscv: vector floating-point classify instructions
> target/riscv: vector floating-point merge instructions
> target/riscv: vector floating-point/integer type-convert instructions
> target/riscv: widening floating-point/integer type-convert
> instructions
> target/riscv: narrowing floating-point/integer type-convert
> instructions
> target/riscv: vector single-width integer reduction instructions
> target/riscv: vector wideing integer reduction instructions
> target/riscv: vector single-width floating-point reduction
> instructions
> target/riscv: vector widening floating-point reduction instructions
> target/riscv: vector mask-register logical instructions
> target/riscv: vector mask population count vmpopc
> target/riscv: vmfirst find-first-set mask bit
> target/riscv: set-X-first mask bit
> target/riscv: vector iota instruction
> target/riscv: vector element index instruction
> target/riscv: integer extract instruction
> target/riscv: integer scalar move instruction
> target/riscv: floating-point scalar move instructions
> target/riscv: vector slide instructions
> target/riscv: vector register gather instruction
> target/riscv: vector compress instruction
> target/riscv: configure and turn on vector extension from command line
>
> target/riscv/Makefile.objs | 2 +-
> target/riscv/cpu.c | 50 +
> target/riscv/cpu.h | 82 +-
> target/riscv/cpu_bits.h | 15 +
> target/riscv/csr.c | 75 +-
> target/riscv/fpu_helper.c | 33 +-
> target/riscv/helper.h | 1069 +++++
> target/riscv/insn32-64.decode | 11 +
> target/riscv/insn32.decode | 372 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 2888 +++++++++++++
> target/riscv/internals.h | 41 +
> target/riscv/translate.c | 27 +-
> target/riscv/vector_helper.c | 4899 +++++++++++++++++++++++
> 13 files changed, 9520 insertions(+), 44 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
> create mode 100644 target/riscv/internals.h
> create mode 100644 target/riscv/vector_helper.c
>
> --
> 2.23.0
>
>
- [PATCH v12 53/61] target/riscv: vector iota instruction, (continued)
- [PATCH v12 53/61] target/riscv: vector iota instruction, LIU Zhiwei, 2020/07/01
- [PATCH v12 54/61] target/riscv: vector element index instruction, LIU Zhiwei, 2020/07/01
- [PATCH v12 55/61] target/riscv: integer extract instruction, LIU Zhiwei, 2020/07/01
- [PATCH v12 56/61] target/riscv: integer scalar move instruction, LIU Zhiwei, 2020/07/01
- [PATCH v12 57/61] target/riscv: floating-point scalar move instructions, LIU Zhiwei, 2020/07/01
- [PATCH v12 58/61] target/riscv: vector slide instructions, LIU Zhiwei, 2020/07/01
- [PATCH v12 59/61] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/07/01
- [PATCH v12 60/61] target/riscv: vector compress instruction, LIU Zhiwei, 2020/07/01
- [PATCH v12 61/61] target/riscv: configure and turn on vector extension from command line, LIU Zhiwei, 2020/07/01
- Re: [PATCH v12 00/61] target/riscv: support vector extension v0.7.1, no-reply, 2020/07/01
- Re: [PATCH v12 00/61] target/riscv: support vector extension v0.7.1,
Alistair Francis <=