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Re: [RFC 09/65] target/riscv: rvv-0.9: add vlenb register
From: |
Richard Henderson |
Subject: |
Re: [RFC 09/65] target/riscv: rvv-0.9: add vlenb register |
Date: |
Fri, 10 Jul 2020 10:31:02 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 228b9bdb5d..871c2ddfa1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -317,6 +317,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> env->mcause = 0;
> env->pc = env->resetvec;
> + env->vlenb = cpu->cfg.vlen >> 3;
> #endif
> cs->exception_index = EXCP_NONE;
> env->load_res = -1;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c02690ed0d..81c85bf4c2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -111,6 +111,7 @@ struct CPURISCVState {
> target_ulong vl;
> target_ulong vstart;
> target_ulong vtype;
> + target_ulong vlenb;
I don't see that you need this. The field is read-only, so the read_vlenb
function can just return
env_archcpu(env)->cfg.vlen >> 3
directly.
r~
- Re: [RFC 04/65] target/riscv: fix vill bit index in vtype register, (continued)
- [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, frank . chang, 2020/07/10
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/10
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/14
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/10
- Re: [RFC 09/65] target/riscv: rvv-0.9: add vlenb register,
Richard Henderson <=
[RFC 13/65] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/10
[RFC 15/65] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/10
[RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/10
[RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation, frank . chang, 2020/07/10
[RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction, frank . chang, 2020/07/10
[RFC 28/65] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/10
[RFC 32/65] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/10
[RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions, frank . chang, 2020/07/10