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[PATCH 05/11] riscv: Add RV64D instructions description
From: |
LIU Zhiwei |
Subject: |
[PATCH 05/11] riscv: Add RV64D instructions description |
Date: |
Sun, 12 Jul 2020 00:16:49 +0800 |
For supporting multi-precison, split all 32 fp registers into two groups.
The RV64D instructions will use only the 16 fp registers selected by
gfp64().
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
rv64.risu | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/rv64.risu b/rv64.risu
index 0dcc9a1..a6fa9fc 100644
--- a/rv64.risu
+++ b/rv64.risu
@@ -364,3 +364,103 @@ FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
+
+@RV64D
+
+FLD RISCV imm:12 rs1:5 011 rd:5 0000111 \
+!constraints { gbase($rs1) && gfp64($rd); } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+FSD RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100111 \
+!constraints { gbase($rs1) && gfp64($rs2); } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+FMADD_D RISCV rs3:5 01 rs2:5 rs1:5 rm:3 rd:5 1000011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); }
+
+FMSUB_D RISCV rs3:5 01 rs2:5 rs1:5 rm:3 rd:5 1000111 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); }
+
+FNMSUB_D RISCV rs3:5 01 rs2:5 rs1:5 rm:3 rd:5 1001011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); }
+
+FNMADD_D RISCV rs3:5 01 rs2:5 rs1:5 rm:3 rd:5 1001111 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); }
+
+FADD_D RISCV 0000001 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); }
+
+FSUB_D RISCV 0000101 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); }
+
+FMUL_D RISCV 0001001 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); }
+
+FDIV_D RISCV 0001101 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); }
+
+FSQRT_D RISCV 0101101 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rd) && grm($rm); }
+
+FSGNJ_D RISCV 0010001 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); }
+
+FSGNJN_D RISCV 0010001 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); }
+
+FSGNJX_D RISCV 0010001 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); }
+
+FMIN_D RISCV 0010101 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); }
+
+FMAX_D RISCV 0010101 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); }
+
+FCVT_S_D RISCV 0100000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rd) && grm($rm); }
+
+FCVT_D_S RISCV 0100001 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp64($rs1) && gfp64($rd) && grm($rm); }
+
+FEQ_D RISCV 1010001 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1) && gfp64($rs1); }
+
+FLT_D RISCV 1010001 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1) && gfp64($rs1); }
+
+FLE_D RISCV 1010001 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1) && gfp64($rs1); }
+
+FCLASS_D RISCV 1110001 00000 rs1:5 001 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1); }
+
+FCVT_W_D RISCV 1100001 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1) && grm($rm); }
+
+FCVT_WU_D RISCV 1100001 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1) && grm($rm); }
+
+FCVT_D_W RISCV 1101001 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp64($rd) && grm($rm); }
+
+FCVT_D_WU RISCV 1101001 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp64($rd) && grm($rm); }
+
+FCVT_L_D RISCV 1100001 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1) && grm($rm); }
+
+FCVT_LU_D RISCV 1100001 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1) && grm($rm); }
+
+FCVT_D_L RISCV 1101001 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp64($rd) && grm($rm); }
+
+FCVT_D_LU RISCV 1101001 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp64($rd) && grm($rm); }
+
+FMV_D_X RISCV 1111001 00000 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rs1) && gfp64($rd); }
+
+FMV_X_D RISCV 1110001 00000 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rd) && gfp64($rs1); }
--
2.23.0
- [PATCH 00/11] RISC-V risu porting, LIU Zhiwei, 2020/07/11
- [PATCH 02/11] riscv: Add RV64M instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 04/11] riscv: Add RV64F instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 05/11] riscv: Add RV64D instructions description,
LIU Zhiwei <=
- [PATCH 06/11] riscv: Add RV64C instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 08/11] riscv: Add standard test case, LIU Zhiwei, 2020/07/11
- [PATCH 10/11] riscv: Implement payload load interfaces, LIU Zhiwei, 2020/07/11
- [PATCH 11/11] riscv: Add configure script, LIU Zhiwei, 2020/07/11
- [PATCH 03/11] riscv: Add RV64A instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 07/11] riscv: Generate payload scripts, LIU Zhiwei, 2020/07/11
- [PATCH 09/11] riscv: Define riscv struct reginfo, LIU Zhiwei, 2020/07/11
- [PATCH 01/11] riscv: Add RV64I instructions description, LIU Zhiwei, 2020/07/11
- Re: [PATCH 00/11] RISC-V risu porting, LIU Zhiwei, 2020/07/21