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Re: [PATCH] hw/riscv: sifive_e: Correct debug block size
From: |
Alistair Francis |
Subject: |
Re: [PATCH] hw/riscv: sifive_e: Correct debug block size |
Date: |
Tue, 21 Jul 2020 08:12:42 -0700 |
On Thu, Jul 16, 2020 at 2:31 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Currently the debug region size is set to 0x100, but according to
> FE310-G000 and FE310-G002 manuals:
>
> FE310-G000: 0x100 - 0xFFF
> FE310-G002: 0x0 - 0xFFF
>
> Change the size to 0x1000 that applies to both.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_e.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 7bb97b4..c8b0604 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -54,7 +54,7 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } sifive_e_memmap[] = {
> - [SIFIVE_E_DEBUG] = { 0x0, 0x100 },
> + [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
> [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
> [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
> [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
> --
> 2.7.4
>
>