[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector m
From: |
frank . chang |
Subject: |
[RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation |
Date: |
Wed, 22 Jul 2020 17:15:52 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 0.9.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 32 +++++++++++++++----------
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++-
2 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a650df0441..446ce1a667 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,8 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
+#include "internals.h"
+
#define TCG_GUEST_DEFAULT_MO 0
#define TYPE_RISCV_CPU "riscv-cpu"
@@ -379,20 +381,14 @@ FIELD(TB_FLAGS, VMA, 12, 1)
/* Skip MSTATUS_FS (0x6000) fields */
FIELD(TB_FLAGS, VILL, 15, 1)
-/*
- * A simplification for VLMAX
- * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
- * = (VLEN << LMUL) / (8 << SEW)
- * = (VLEN << LMUL) >> (SEW + 3)
- * = VLEN >> (SEW + 3 - LMUL)
- */
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
{
uint8_t sew, lmul;
-
sew = FIELD_EX64(vtype, VTYPE, VSEW);
- lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
- return cpu->cfg.vlen >> (sew + 3 - lmul);
+ lmul = (FIELD_EX64(vtype, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(vtype, VTYPE, VLMUL);
+ float flmul = flmul_table[lmul];
+ return cpu->cfg.vlen * flmul / (1 << (sew + 3));
}
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
@@ -404,13 +400,23 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
*env, target_ulong *pc,
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
+ /*
+ * If env->vl equals to VLMAX, we can use generic vector operation
+ * expanders (GVEC) to accerlate the vector operations.
+ * However, as LMUL could be a fractional number. The maximum
+ * vector size can be operated might be less than 8 bytes,
+ * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
+ * only when maxsz >= 8 bytes.
+ */
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
- bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+ uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+ uint32_t maxsz = vlmax * (1 << sew);
+ bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl)
+ && (maxsz >= 8);
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
- flags = FIELD_DP32(flags, TB_FLAGS, SEW,
- FIELD_EX64(env->vtype, VTYPE, VSEW));
+ flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
(FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2)
| FIELD_EX64(env->vtype, VTYPE, VLMUL));
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 4274daf08e..89209a5d18 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1270,7 +1270,16 @@ GEN_VEXT_TRANS(vamomaxuei64_v, 64, 8, rwdvm, amo_op,
amo_check)
/*
*** Vector Integer Arithmetic Instructions
*/
-#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
+
+/*
+ * MAXSZ returns the maximum vector size can be operated in bytes,
+ * which is used in GVEC IR when vl_eq_vlmax flag is set to true
+ * to accerlate vector operation.
+ */
+static inline uint32_t MAXSZ(DisasContext *s)
+{
+ return (s->vlen >> 3) * s->flmul;
+}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
--
2.17.1
- Re: [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions, (continued)
- [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/22
- [RFC v2 23/76] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/22
- [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/07/22
- [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load, frank . chang, 2020/07/22
- [RFC v2 26/76] target/riscv: rvv-0.9: amo operations, frank . chang, 2020/07/22
- [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/22
- [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/22
- [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation,
frank . chang <=
- [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction, frank . chang, 2020/07/22
- [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/22
- [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/22
- [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/22
- [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/22