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Re: [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9
From: |
Richard Henderson |
Subject: |
Re: [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9 |
Date: |
Wed, 22 Jul 2020 09:13:32 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 7/22/20 2:15 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.c | 24 ++++++++++++++++++------
> target/riscv/cpu.h | 2 ++
> 2 files changed, 20 insertions(+), 6 deletions(-)
I think you can squash this with patch 1, just so you don't have to churn
functions like set_vext_version. Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
[RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9, frank . chang, 2020/07/22
- Re: [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9,
Richard Henderson <=
[RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/22
[RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/22
[RFC v2 05/76] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/22
[RFC v2 06/76] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/22
[RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/07/22
[RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field, frank . chang, 2020/07/22
[RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, frank . chang, 2020/07/22