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[PATCH v2 6/7] target/riscv: Clean up fmv.w.x
From: |
Richard Henderson |
Subject: |
[PATCH v2 6/7] target/riscv: Clean up fmv.w.x |
Date: |
Thu, 23 Jul 2020 17:28:06 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Use tcg_gen_extu_tl_i64 to avoid the ifdef.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvf.inc.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index f9a9e0643a..0d04677a02 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -406,11 +406,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
-#endif
+ tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
mark_fs_dirty(ctx);
--
2.25.1
- Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers, (continued)
[PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c, Richard Henderson, 2020/07/23
[PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers, Richard Henderson, 2020/07/23
[PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c, Richard Henderson, 2020/07/23
[PATCH v2 6/7] target/riscv: Clean up fmv.w.x,
Richard Henderson <=
[PATCH v2 7/7] target/riscv: check before allocating TCG temps, Richard Henderson, 2020/07/23
Re: [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison, LIU Zhiwei, 2020/07/23
Re: [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison, Alistair Francis, 2020/07/27