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Re: [PATCH v2 5/5] [RISCV_PM] Implement address masking functions requir
From: |
Richard Henderson |
Subject: |
Re: [PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension |
Date: |
Thu, 15 Oct 2020 10:07:26 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 10/15/20 8:21 AM, Alexey Baturo wrote:
> + switch (priv) {
> + case PRV_U:
> + pm_enabled = env->mmte & U_PM_ENABLE;
> + break;
> + case PRV_S:
> + pm_enabled = env->mmte & S_PM_ENABLE;
> + break;
> + case PRV_M:
> + pm_enabled = env->mmte & M_PM_ENABLE;
> + break;
> + default:
> + assert(0 && "Unreachable");
g_assert_not_reached();
> + /* PointerMasking extension */
> + uint8_t pm_enabled;
bool
> + if (s->pm_enabled == 0) {
!s->pm_enabled
> + if (riscv_has_ext(env, RVJ)) {
> + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
> + int priv = cpu_mmu_index(env, false);
> + ctx->pm_mask = pm_mask[priv];
> + ctx->pm_base = pm_base[priv];
> + } else {
> + ctx->pm_enabled = 0;
> + }
Don't need the if. And should it in fact be placed outside the ifdef? This
shouldn't be related to !CONFIG_USER_ONLY here and nowhere else.
r~
- [PATCH v2 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode, (continued)
[PATCH v2 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2020/10/15
[PATCH v2 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2020/10/15
[PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2020/10/15
- Re: [PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension,
Richard Henderson <=