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[PATCH v6 1/6] [RISCV_PM] Add J-extension into RISC-V
From: |
Alexey Baturo |
Subject: |
[PATCH v6 1/6] [RISCV_PM] Add J-extension into RISC-V |
Date: |
Thu, 22 Oct 2020 11:04:35 +0300 |
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f457..4e305249b3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -516,6 +516,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de275782e6..eca611a367 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -66,6 +66,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -277,6 +278,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_counters;
bool ext_ifencei;
--
2.20.1
- [PATCH v6 0/6] RISC-V Pointer Masking implementation, Alexey Baturo, 2020/10/22
- [PATCH v6 1/6] [RISCV_PM] Add J-extension into RISC-V,
Alexey Baturo <=
- [PATCH v6 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2020/10/22
- [PATCH v6 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2020/10/22
- [PATCH v6 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode, Alexey Baturo, 2020/10/22
- [PATCH v6 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2020/10/22
- [PATCH v6 6/6] [RISCV_PM] Allow experimental J-ext to be turned on, Alexey Baturo, 2020/10/22
- Re: [PATCH v6 0/6] RISC-V Pointer Masking implementation, Alistair Francis, 2020/10/23