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Re: [PATCH V3 4/6] target/riscv: Add H extension state description
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH V3 4/6] target/riscv: Add H extension state description |
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Date: |
Fri, 23 Oct 2020 17:00:17 -0700 |
On Fri, Oct 23, 2020 at 2:16 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> In the case of supporting H extension, add H extension description
> to vmstate_riscv_cpu.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/machine.c | 47 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index fc1461d88e..ae60050898 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -68,6 +68,52 @@ static const VMStateDescription vmstate_pmp = {
> }
> };
>
> +static bool hyper_needed(void *opaque)
> +{
> + RISCVCPU *cpu = opaque;
> + CPURISCVState *env = &cpu->env;
> +
> + return riscv_has_ext(env, RVH);
> +}
> +
> +static const VMStateDescription vmstate_hyper = {
> + .name = "cpu/hyper",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .needed = hyper_needed,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> + VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> + VMSTATE_UINTTL(env.hideleg, RISCVCPU),
> + VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> + VMSTATE_UINTTL(env.htval, RISCVCPU),
> + VMSTATE_UINTTL(env.htinst, RISCVCPU),
> + VMSTATE_UINTTL(env.hgatp, RISCVCPU),
> + VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> +
> + VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> + VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> + VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
> + VMSTATE_UINTTL(env.vsepc, RISCVCPU),
> + VMSTATE_UINTTL(env.vscause, RISCVCPU),
> + VMSTATE_UINTTL(env.vstval, RISCVCPU),
> + VMSTATE_UINTTL(env.vsatp, RISCVCPU),
> +
> + VMSTATE_UINTTL(env.mtval2, RISCVCPU),
> + VMSTATE_UINTTL(env.mtinst, RISCVCPU),
> +
> + VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
> + VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
> +
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> .version_id = 1,
> @@ -119,6 +165,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> },
> .subsections = (const VMStateDescription * []) {
> &vmstate_pmp,
> + &vmstate_hyper,
> NULL
> }
> };
> --
> 2.19.1
>
>
- [PATCH V3 0/6] Support RISC-V migration, Yifei Jiang, 2020/10/23
- [PATCH V3 2/6] target/riscv: Add basic vmstate description of CPU, Yifei Jiang, 2020/10/23
- [PATCH V3 4/6] target/riscv: Add H extension state description, Yifei Jiang, 2020/10/23
- Re: [PATCH V3 4/6] target/riscv: Add H extension state description,
Alistair Francis <=
- [PATCH V3 5/6] target/riscv: Add V extension state description, Yifei Jiang, 2020/10/23
- [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate, Yifei Jiang, 2020/10/23
- [PATCH V3 3/6] target/riscv: Add PMP state description, Yifei Jiang, 2020/10/23
- [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Yifei Jiang, 2020/10/23