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Re: [PATCH V4 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into o
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH V4 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit |
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Date: |
Tue, 27 Oct 2020 11:40:01 -0700 |
On Tue, Oct 27, 2020 at 11:47 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/26/20 4:55 AM, Yifei Jiang wrote:
> > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
> > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ",
> > (target_ulong)env->mstatus);
>
> This is truncating mstatus to target_ulong, i.e. breaking the output for
> riscv32. You should use PRIx64 and print the whole 64-bit value.
That is what we want to do though. For RV32 the mstatus CSR is only
32-bits, where the upper 32-bit are stored in mstatush (the top
32-bits of QEMU's internal mstatus).
Alistair
>
>
> r~
>
- [PATCH V4 0/6] Support RISC-V migration, Yifei Jiang, 2020/10/26
- [PATCH V4 3/6] target/riscv: Add PMP state description, Yifei Jiang, 2020/10/26
- [PATCH V4 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Yifei Jiang, 2020/10/26
- [PATCH V4 4/6] target/riscv: Add H extension state description, Yifei Jiang, 2020/10/26
- [PATCH V4 5/6] target/riscv: Add V extension state description, Yifei Jiang, 2020/10/26
- [PATCH V4 2/6] target/riscv: Add basic vmstate description of CPU, Yifei Jiang, 2020/10/26
- [PATCH V4 6/6] target/riscv: Add sifive_plic vmstate, Yifei Jiang, 2020/10/26
- Re: [PATCH V4 0/6] Support RISC-V migration, Alistair Francis, 2020/10/27