[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 08/10] hw/riscv: microchip_pfsoc: Map the reserved memory
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 |
Date: |
Wed, 28 Oct 2020 07:51:48 -0700 |
On Tue, Oct 27, 2020 at 10:36 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Somehow HSS needs to access address 0 [1] for the DDR calibration data
> which is in the chipset's reserved memory. Let's map it.
>
> [1] See the config_copy() calls in various places in ddr_setup() in
> the HSS source codes.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - change to map the reserved memory at address 0 instead of debug memory
>
> hw/riscv/microchip_pfsoc.c | 11 ++++++++++-
> include/hw/riscv/microchip_pfsoc.h | 1 +
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index bc908e0..44a8473 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -90,7 +90,8 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } microchip_pfsoc_memmap[] = {
> - [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 },
> + [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
> + [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
> [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
> [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
> [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
> @@ -176,6 +177,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
> Error **errp)
> MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
> const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
> MemoryRegion *system_memory = get_system_memory();
> + MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
> MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *envm_data = g_new(MemoryRegion, 1);
> @@ -195,6 +197,13 @@ static void microchip_pfsoc_soc_realize(DeviceState
> *dev, Error **errp)
> qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
> qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
>
> + /* Reserved Memory at address 0 */
> + memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem",
> + memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_RSVD0].base,
> + rsvd0_mem);
> +
> /* E51 DTIM */
> memory_region_init_ram(e51_dtim_mem, NULL,
> "microchip.pfsoc.e51_dtim_mem",
> memmap[MICROCHIP_PFSOC_E51_DTIM].size,
> &error_fatal);
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index 245c82d..f34a6b3 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -74,6 +74,7 @@ typedef struct MicrochipIcicleKitState {
> TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
>
> enum {
> + MICROCHIP_PFSOC_RSVD0,
> MICROCHIP_PFSOC_DEBUG,
> MICROCHIP_PFSOC_E51_DTIM,
> MICROCHIP_PFSOC_BUSERR_UNIT0,
> --
> 2.7.4
>
>
- [PATCH v2 01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, (continued)
- [PATCH v2 01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Bin Meng, 2020/10/28
- [PATCH v2 02/10] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Bin Meng, 2020/10/28
- [PATCH v2 03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Bin Meng, 2020/10/28
- [PATCH v2 04/10] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Bin Meng, 2020/10/28
- [PATCH v2 06/10] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Bin Meng, 2020/10/28
- [PATCH v2 05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Bin Meng, 2020/10/28
- [PATCH v2 07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Bin Meng, 2020/10/28
- [PATCH v2 08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Bin Meng, 2020/10/28
- Re: [PATCH v2 08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0,
Alistair Francis <=
- [PATCH v2 09/10] hw/riscv: microchip_pfsoc: Correct DDR memory map, Bin Meng, 2020/10/28
- [PATCH v2 10/10] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Bin Meng, 2020/10/28
- Re: [PATCH v2 00/10] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box, Alistair Francis, 2020/10/28