From: Emmanuel Blot <emmanuel.blot@sifive.com>
To: qemu-riscv@nongnu.org
Cc: Emmanuel Blot <emmanuel.blot@sifive.com>
Subject: [PATCH 0/2] Fix PLIC issues
Date: Tue, 3 Nov 2020 16:29:17 +0100
PLIC may trigger a buffer overflow when the highest IRQ source is
signalled.
IRQ0 being treated as "non-existent" IRQ, N+1 slot should be allocated
and
handled.
Emmanuel Blot (2):
hw/riscv: plic: Fix highest IRQ source slot
hw/riscv: plic: Make IRQ slot 0 part of the IRQ priority array
hw/intc/sifive_plic.c | 27 +++++++++++++++------------
include/hw/riscv/microchip_pfsoc.h | 2 +-
include/hw/riscv/sifive_e.h | 2 +-
include/hw/riscv/sifive_u.h | 2 +-
include/hw/riscv/virt.h | 2 +-
5 files changed, 19 insertions(+), 16 deletions(-)
--
2.28.0