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Re: [RFC v2 10/15] target/riscv: rvb: rotate (left/right)
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v2 10/15] target/riscv: rvb: rotate (left/right) |
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Date: |
Wed, 16 Dec 2020 10:39:31 -0600 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_ror(DisasContext *ctx, arg_ror *a)
> {
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, &tcg_gen_rotr_tl);
> +}
Use gen_shift.
> +static bool trans_rori(DisasContext *ctx, arg_rori *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + TCGv source1 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_rotri_tl(source1, source1, a->shamt);
> + gen_set_gpr(a->rd, source1);
Use gen_shifti.
> +static bool trans_rol(DisasContext *ctx, arg_rol *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, &tcg_gen_rotl_tl);
> +}
Use gen_shift.
> +static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, &gen_rorw);
> +}
> +
> +static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= 32) {
> + return false;
> + }
Test is impossible due to @sh5.
> + if (a->shamt == 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> + tcg_gen_ext32s_tl(t, t);
> + gen_set_gpr(a->rd, t);
> + tcg_temp_free(t);
> + return true;
> + }
Why do you need this special case? The general expansion would appear to work
fine, and surely this needs no special optimization.
r~
- Re: [RFC v2 05/15] target/riscv: rvb: pack two words into one register, (continued)
- [RFC v2 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/12/15
- [RFC v2 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/12/15
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/12/15
- [RFC v2 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/12/15
- [RFC v2 10/15] target/riscv: rvb: rotate (left/right), frank . chang, 2020/12/15
- Re: [RFC v2 10/15] target/riscv: rvb: rotate (left/right),
Richard Henderson <=
- [RFC v2 11/15] target/riscv: rvb: generalized reverse, frank . chang, 2020/12/15
- [RFC v2 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/12/15
- [RFC v2 13/15] target/riscv: rvb: address calculation, frank . chang, 2020/12/15
- [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend, frank . chang, 2020/12/15
- [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line, frank . chang, 2020/12/15