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[PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing
From: |
frank . chang |
Subject: |
[PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers |
Date: |
Tue, 12 Jan 2021 17:38:44 +0800 |
From: Frank Chang <frank.chang@sifive.com>
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7a6554447af..30f1593efb1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,6 +56,11 @@ static int fs(CPURISCVState *env, int csrno)
static int vs(CPURISCVState *env, int csrno)
{
if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+#endif
return 0;
}
return -1;
--
2.17.1
- [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status, (continued)
- [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/01/12
- [PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/01/12
- [PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/01/12
- [PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/01/12
- [PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/01/12
- [PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers,
frank . chang <=
- [PATCH v6 11/72] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/01/12
- [PATCH v6 12/72] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/01/12
- [PATCH v6 13/72] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/01/12
- [PATCH v6 15/72] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/01/12
- [PATCH v6 14/72] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/01/12