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Re: [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support |
Date: |
Thu, 28 Jan 2021 12:56:39 -0800 |
On Mon, Jan 25, 2021 at 10:01 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This adds the ISSI SPI flash support. The number of dummy cycles in
> fast read, fast read dual output and fast read quad output commands
> is currently using the default 8. Likewise, the same default value
> is used for fast read dual/quad I/O command. Per the datasheet [1],
> the number of dummy cycles is configurable, but this is not modeled
> at present.
>
> For flash whose size is larger than 16 MiB, the sequence of 3-byte
> address along with EXTADD bit in the bank address register (BAR) is
> not supported. We assume that guest software always uses op codes
> with 4-byte address sequence. Fortunately, this is the case for both
> U-Boot and Linux spi-nor drivers.
>
> QPI (Quad Peripheral Interface) that supports 2-cycle instruction
> has different default values for dummy cycles of fast read family
> commands, and is unsupported at the time being.
>
> [1] http://www.issi.com/WW/pdf/25LP-WP256.pdf
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Mention QPI (Quad Peripheral Interface) mode is not supported
>
> hw/block/m25p80.c | 44 +++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index b744a58d1c..217c130f56 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -412,6 +412,7 @@ typedef enum {
> MAN_NUMONYX,
> MAN_WINBOND,
> MAN_SST,
> + MAN_ISSI,
> MAN_GENERIC,
> } Manufacturer;
>
> @@ -487,6 +488,8 @@ static inline Manufacturer get_man(Flash *s)
> return MAN_MACRONIX;
> case 0xBF:
> return MAN_SST;
> + case 0x9D:
> + return MAN_ISSI;
> default:
> return MAN_GENERIC;
> }
> @@ -706,6 +709,9 @@ static void complete_collecting_data(Flash *s)
> case MAN_SPANSION:
> s->quad_enable = !!(s->data[1] & 0x02);
> break;
> + case MAN_ISSI:
> + s->quad_enable = extract32(s->data[0], 6, 1);
> + break;
> case MAN_MACRONIX:
> s->quad_enable = extract32(s->data[0], 6, 1);
> if (s->len > 1) {
> @@ -895,6 +901,19 @@ static void decode_fast_read_cmd(Flash *s)
> SPANSION_DUMMY_CLK_LEN
> );
> break;
> + case MAN_ISSI:
> + /*
> + * The Fast Read instruction code is followed by address bytes and
> + * dummy cycles, transmitted via the SI line.
> + *
> + * The number of dummy cycles is configurable but this is currently
> + * unmodeled, hence the default value 8 is used.
> + *
> + * QPI (Quad Peripheral Interface) mode has different default value
> + * of dummy cycles, but this is unsupported at the time being.
> + */
> + s->needed_bytes += 1;
> + break;
> default:
> break;
> }
> @@ -934,6 +953,16 @@ static void decode_dio_read_cmd(Flash *s)
> break;
> }
> break;
> + case MAN_ISSI:
> + /*
> + * The Fast Read Dual I/O instruction code is followed by address
> bytes
> + * and dummy cycles, transmitted via the IO1 and IO0 line.
> + *
> + * The number of dummy cycles is configurable but this is currently
> + * unmodeled, hence the default value 4 is used.
> + */
> + s->needed_bytes += 1;
> + break;
> default:
> break;
> }
> @@ -974,6 +1003,19 @@ static void decode_qio_read_cmd(Flash *s)
> break;
> }
> break;
> + case MAN_ISSI:
> + /*
> + * The Fast Read Quad I/O instruction code is followed by address
> bytes
> + * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line.
> + *
> + * The number of dummy cycles is configurable but this is currently
> + * unmodeled, hence the default value 6 is used.
> + *
> + * QPI (Quad Peripheral Interface) mode has different default value
> + * of dummy cycles, but this is unsupported at the time being.
> + */
> + s->needed_bytes += 3;
> + break;
> default:
> break;
> }
> @@ -1132,7 +1174,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
>
> case RDSR:
> s->data[0] = (!!s->write_enable) << 1;
> - if (get_man(s) == MAN_MACRONIX) {
> + if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
> s->data[0] |= (!!s->quad_enable) << 6;
> }
> if (get_man(s) == MAN_SST) {
> --
> 2.25.1
>
>
- [PATCH v3 0/9] hw/riscv: sifive_u: Add missing SPI support, Bin Meng, 2021/01/26
- [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support, Bin Meng, 2021/01/26
- Re: [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support,
Alistair Francis <=
- [PATCH v3 2/9] hw/block: m25p80: Add various ISSI flash information, Bin Meng, 2021/01/26
- [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support, Bin Meng, 2021/01/26
- [PATCH v3 4/9] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Bin Meng, 2021/01/26
- [PATCH v3 5/9] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Bin Meng, 2021/01/26
- [PATCH v3 6/9] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value, Bin Meng, 2021/01/26
- [PATCH v3 7/9] docs/system: Sort targets in alphabetical order, Bin Meng, 2021/01/26
- [PATCH v3 8/9] docs/system: Add RISC-V documentation, Bin Meng, 2021/01/26
- [PATCH v3 9/9] docs/system: riscv: Add documentation for sifive_u machine, Bin Meng, 2021/01/26