Re: [PATCH] target/riscv: Align the data type of reset vector address

[Alistair Francis]

On Tue, Mar 23, 2021 at 5:15 AM Dylan Jhong <dylan@andestech.com> wrote:
>
> Although the AE350 has not been upstream (preparing for v2),
> the reset vector of the AE350 is known to be at the 2G position,
> so this patch is corrected in advance.
>
> Signed-off-by: Dylan Jhong <dylan@andestech.com>
> Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
> ---
>  target/riscv/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2a990f6253..0236abf169 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature)
>      env->features |= (1ULL << feature);
>  }
>
> -static void set_resetvec(CPURISCVState *env, int resetvec)
> +static void set_resetvec(CPURISCVState *env, uint64_t resetvec)

resetvec in env is a target_ulong so this should be as well (instead
of a uint64_t).

Alistair

>  {
>  #ifndef CONFIG_USER_ONLY
>      env->resetvec = resetvec;
> --
> 2.17.1
>
>