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[PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro |
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Date: |
Fri, 2 Apr 2021 16:02:40 -0400 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 30 +++++++++++++++++++++++-------
target/riscv/csr.c | 33 ++++++++++++++++++++++++---------
target/riscv/monitor.c | 22 +++++++++++++++++-----
4 files changed, 64 insertions(+), 32 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index dd643d0f63..6a816ce9c2 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -452,17 +452,6 @@
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
-#if defined(TARGET_RISCV32)
-#define SATP_MODE SATP32_MODE
-#define SATP_ASID SATP32_ASID
-#define SATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define SATP_MODE SATP64_MODE
-#define SATP_ASID SATP64_ASID
-#define SATP_PPN SATP64_PPN
-#endif
-
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
#define VM_1_09_MBARE 0
#define VM_1_09_MBB 1
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6446af5de0..7ae9352d80 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -403,11 +403,21 @@ static int get_physical_address(CPURISCVState *env,
hwaddr *physical,
if (first_stage == true) {
if (use_background) {
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->vsatp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP64_MODE);
+ }
} else {
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->satp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
}
widened = 0;
} else {
@@ -622,9 +632,15 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
CPUState *cs = env_cpu(env);
int page_fault_exceptions;
if (first_stage) {
- page_fault_exceptions =
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ if (riscv_cpu_is_32bit(env)) {
+ page_fault_exceptions =
+ get_field(env->satp, SATP32_MODE) != VM_1_10_MBARE &&
+ !pmp_violation;
+ } else {
+ page_fault_exceptions =
+ get_field(env->satp, SATP64_MODE) != VM_1_10_MBARE &&
+ !pmp_violation;
+ }
} else {
if (riscv_cpu_is_32bit(env)) {
page_fault_exceptions =
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6052b2d6e9..b0ebaa029e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -930,16 +930,31 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return 0;
}
- if (validate_vm(env, get_field(val, SATP_MODE)) &&
- ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
- {
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- } else {
- if ((val ^ env->satp) & SATP_ASID) {
- tlb_flush(env_cpu(env));
+ if (riscv_cpu_is_32bit(env)) {
+ if (validate_vm(env, get_field(val, SATP32_MODE)) &&
+ ((val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN)))
+ {
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ } else {
+ if ((val ^ env->satp) & SATP32_ASID) {
+ tlb_flush(env_cpu(env));
+ }
+ env->satp = val;
+ }
+ }
+ } else {
+ if (validate_vm(env, get_field(val, SATP64_MODE)) &&
+ ((val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN)))
+ {
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ } else {
+ if ((val ^ env->satp) & SATP64_ASID) {
+ tlb_flush(env_cpu(env));
+ }
+ env->satp = val;
}
- env->satp = val;
}
}
return 0;
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index e51188f919..f7e6ea72b3 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
target_ulong last_size;
int last_attr;
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
- vm = get_field(env->satp, SATP_MODE);
switch (vm) {
case VM_1_10_SV32:
levels = 2;
@@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (!(env->satp & SATP_MODE)) {
- monitor_printf(mon, "No translation or protection\n");
- return;
+ if (riscv_cpu_is_32bit(env)) {
+ if (!(env->satp & SATP32_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
+ } else {
+ if (!(env->satp & SATP64_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
}
mem_info_svxx(mon, env);
--
2.31.0