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[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructi
From: |
frank . chang |
Subject: |
[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions |
Date: |
Mon, 19 Apr 2021 13:56:10 +0800 |
From: Frank Chang <frank.chang@sifive.com>
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
In RISC-V Unprivileged ISA spec:
The fused multiply-add instructions must set the invalid
operation exception flag when the multiplicands are Inf and
zero, even when the addend is a quiet NaN.
This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat-specialize.c.inc | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index c2f87addb25..9c37265e20b 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -624,6 +624,23 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
} else {
return 1;
}
+#elif defined(TARGET_RISCV)
+ /*
+ * For RISC-V, InvalidOp is set when multiplicands are Inf and zero
+ * and returns default NaN.
+ */
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ return 3;
+ }
+
+ if (is_nan(a_cls)) {
+ return 0;
+ } else if (is_nan(b_cls)) {
+ return 1;
+ } else {
+ return 2;
+ }
#elif defined(TARGET_XTENSA)
/*
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
--
2.17.1
- [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions,
frank . chang <=