[RFC] target/riscv: generated RISCV isa string and subset naming convention

[Emmanuel Blot]

The riscv_isa_string function deals with all the misa bits the same way.
However, it seems froom the specification that bits should not be 
equally
represented in the isa string.

For example:

- user mode ISA extension does not seem to be part of the isa string, 
only N
  (user mode interrupt) does.
- S/H/X/Z extensions should be suffixed with an alphabetical name.

Moreover the table 27.1 documents a canonical order that is slightly
different from the one initially implemented.

Should we simplify this string?
This string is used to generate the DTB riscv,isa compatible string.

ref: The RISC-V Instruction Set Manual Volume I: Unprivileged ISA,
Subset Naming Convention section 27.11
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20210402-1271737/riscv-spec.pdf


---
 target/riscv/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b6..4eadd9b9fc1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -32,7 +32,7 @@

 /* RISC-V CPU definitions */

-static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
+static const char riscv_exts[] = "IEMAFDQLCBKJTPVN";

 const char * const riscv_int_regnames[] = {
   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   
"x6/t1",
@@ -641,7 +641,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
     char *isa_str = g_new(char, maxlen);
     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", 
TARGET_LONG_BITS);
-    for (i = 0; i < sizeof(riscv_exts); i++) {
+    for (i = 0; i < sizeof(riscv_exts)-1; i++) {
         if (cpu->env.misa & RV(riscv_exts[i])) {
             *p++ = qemu_tolower(riscv_exts[i]);
         }
--
2.31.1